随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。
The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.
对互连寄生电容提取的研究背景进行了简要的介绍。
In this paper, the background of parasitic capacitance extraction of interconnects are briefly introduced.
在3dVL SI互连寄生电容的边界元素法计算中，多孔平面的边界元划分是十分困难的问题。
In the computations of 3d VLSI parasitic interconnect capacitance, it is very difficult to partition the boundary elements on a multi hole surface.
HPC器件的独特结构减少了由于PC B上的互连线路缩短而引起的寄生现象，并通过缩短组件间的距离提高了电路性能。
HPC devices 'unique construction reduces parasitics by shortening interconnecting traces on PCBs and improves circuit performance by decreasing the distance between components.
介绍复杂互连寄生电容器的结构及对其实现虚拟多介质切割的方法。
In this paper, the complex 3D structures of VLSI interconnect capacitors and the virtual cutting method for them are presented.
随着集成电路设计复杂性以及电路工作时钟频率的不断提高，互连与封装等寄生效应对电路的影响越来越大，产生了信号完整性问题。
At very high frequencies, interconnects and packages can only be characterized by a set of sampled data from measurements or electromagnetic simulations over the frequency of interests.
通过分析互连几何参数波动与互连寄生参数的关系，得到其近似的函数关系表达式。
The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters.
通过分析互连几何参数波动与互连寄生参数的关系，得到其近似的函数关系表达式。
The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters.
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