这个概念围绕一个理念，即基本外壳或基础架构应该提供一些基本需求：电源、联网、管理、一条高速总线、冷却设备、以及存储器。
Well, the concept revolves around the idea that the basic shell or infrastructure should provide the bare necessities: power, networking, management, a high-speed bus, cooling, and storage.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.
传统上讲，工作站的吞吐量与其总线和存储器体系结构以及CPU的速度有关。
Traditionally, a workstation's throughput depends on its bus and memory architecture, as well as its CPU speed.
CPU和主板，总线和接口主存储器。
一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
该系统能发挥两种微机的优势，利用总线周期窃用和分散型共享存储器技术，实现紧耦合方式的高速通信。
The system takes advantage of both, computers and can realize high rate communication in tight coupling style, by using bus period stealing and distributional memory sharing.
端口0也是复低位地址和在利用外部程序和数据存储器的数据总线。
Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory.
数据存储传输模块采用PCI总线和FIFO数据存储器对大量的数据进行连续存储传输，保证数据的准确完整。
In data storage transmission modular, we adopt PCI bus line and FIFO data memory carry out succession for plenty of data to storage transmission, guarantee AE signal accurate collecting.
通过外部总线口扩展外部存储器和接口是构成ADSP2106 X应用系统时最基本、最重要的设计。
Its the fundamental and foremost design for constituting an ADSP2106X application system to expand external memories and interfaces by the external bus port of ADSP2106X.
本接口采用存储器访问模式，克服了某些CPU外围通信接口少的缺点，易于实现双CPU间的总线对接，且无需考虑复杂的总线仲裁机制。
This type of bus interface can be accessed by memory mode and be applied to the exchange of data between two hosts, which can overcome the lack of communication interface in some types of CPU.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
The address bus is used by the processor to select a specific memory location or register within a particular peripheral.
对系统的存储器结构、数据通信通道组成和系统总线结构进行了分析；讨论了算法划分、算法的多处理器映射及调度；
The memory structure, constitution of data communication channel and system bus are analyzed, and the algorithm allocating, algorithm mapping and scheduling on the multiprocessor are discussed.
通过禁止中断及禁止能够改变存储 器内容的总线主设备来保留存储器的内容。
The contents of the memory are preserved by disabling interrupts and disabling bus masters capable of causing a change in the contents of the memory.
对微控制器而言，PDIUSBD12看起来就像一个带8位数据总线和一个地址位（占用两个位置）的存储器件。
To a micro-controller, the PDIUSBD12 appears as a memory device 8-bit data bus and 1 address bit (occupying 2 locations).
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
挂接在PC I用户端的存储器可以复用PC I AD总线完成主设备对其进行的读写操作。
The peripheral memory as a PCI slave device can exchange data with the master device based on the model proposed.
本发明揭示用于在总线业务减少的情况下执行存储器块初始化及复制功能的存储器控制器及方法。
A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed.
SDRAM是当今一种流行的高速存储器。通过和普通sdram存储器对比，阐述了WISHBONE总线协议下ddr存储器控制器的设计方法和注意事项，并提出一种提高DDR工作效率的预测机制。
This paper based on the mechanism of DDR-SDRAM, gave a way to construct a DDR-SDRAM controller based on WISHBONE bus protocol, and also introduced a forecast method to improve DDR's performance.
SDRAM是当今一种流行的高速存储器。通过和普通sdram存储器对比，阐述了WISHBONE总线协议下ddr存储器控制器的设计方法和注意事项，并提出一种提高DDR工作效率的预测机制。
This paper based on the mechanism of DDR-SDRAM, gave a way to construct a DDR-SDRAM controller based on WISHBONE bus protocol, and also introduced a forecast method to improve DDR's performance.
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