调制器减少该分频器的量化误差。
A modulator reduces the quantization error of the frequency divider.
最后简单介绍了超高速分频器的应用情况。
Finally, a brief introduction to the applications of the very high speed frequency divider is given.
讨论了输入附加噪声对注锁分频器特性的影响。
提供一种具有双模分频器的相位切换双模除频器。
A phase-switching dual modulus prescaler having a dual modulus divider is provided.
介绍了一种相位开关型分频器电路的噪声分析方法。
This paper describes a noise analysis method for a phase switching frequency divider.
本文向读者介绍电子分频器二分频的原理计算和制作。
This article introduces the reader to the electronic frequency divider of the two - principles calculation and production.
在锁相环频率合成器中，双模前置分频器是一个速度瓶颈。
In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.
新式的四分频器工作于3.5 ~ 13.0GHz频率。
The new divide-by-four device operates across 3.5 ~ 13.0 GHz frequencies.
第一行的显示屏显示脉冲每分钟浓度除非分频器正在使用中。
The first line of the display shows pulses per minute unless a prescaler is in use.
同时，合并两个锁存器的跟踪差分对可以减小分频器的功耗。
The power of divider can be declined by means of combination of the trace differential pairs of these two latches.
改进逻辑结构的双模16/17预分频器提高了电路工作速度。
A 16/17 dual-modulus prescaler with on improved logic structure increases the speed.
四倍分频器电路演化实验结果验证了该方法的可行性与有效性。
Experiment of fourfold frequency divider proved the feasibility and validity of the method.
比较了数字分频器与传统模拟分频器，说明数字分频器更具优点。
The comparison of digital frequency divider and traditional analog frequency divider shows that the former is more superadded.
介绍一种ECL高速程控分频器的逻辑设计、电路设计及研制结果。
The logic and circuit design of a very high speed ECL programmable frequency divider is described.
再生分频器以其优越的相位噪声性能，在频率合成中有着重要作用。
Regenerative dividers play an important role in frequency synthesizer with its low phase noise.
该分频器采用源极耦合场效应管逻辑电路，基本结构与T触发器相同。
The divider is designed in the Source Coupled Logic, with the structure being similar to the t filp flop.
设计一个8位数控分频器，将8位数控分频器扩展为16位数控分频器。
Design an 8-bit digital divider, the 8-bit prescaler extended to 16-bit CNC CNC divider.
比较了同步分频器和异步分频器，表明了异步分频器在高频应用中的特点。
The characteristics of circuits concerning speed and power are compared between the synchronous divider and the asynchronous divider.
简要设计和实现了基于PC的分频器，从硬件的选配，软件的编写和调试。
Summary of the Design and Implementation of PC-based crossover, the matching of hardware, software, the preparation and debug.
对铷频标中的频率合成器内的程序分频器进行了设计，并介绍了改进后的程序分频器。
A programmable divider used in frequency synthesizer of Rb frequency standard is designed, and the improvement of programmable divider is introduced.
提出了一种基于共振隧穿二极管的新型边沿触发d触发器并将之用于构成二进制分频器。
A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider.
该产生器由输入整形、分频器、数字开关移相器、延迟秒形成、本地秒形成等电路组成。
The generator is composed of input shaping circuit, frequency divider circuit, numeric switch phrase shifter circuit, delay second formation circuit, local second formation circuit and so on.
本文主要研究了光子晶体中的点缺陷和线缺陷，以及由缺陷构成的光子晶体波导和分频器。
The purpose of this paper is to study the dot defect and line defect in photonic crystal, waveguide and demultiplexer.
基于相位转换技术的多模分频器由于其在工作频率和功耗中能更好地折中而得到广泛的应用。
Multi-modulus divider(MMD) based on phase-switching technology finds wide application due to good trade-off between operating frequency and power consumption.
具体电路由锁存器、选择器及分频器组成，以CM O S逻辑和源极耦合逻辑(SCL)实现。
The concrete circuits are composed of latches, selectors and frequency dividers. They are implemented with CMOS logic and source coupled logic (SCL).
电路采用12级级联反馈的双模分频器结构，可以实现小于或等于8 191分频的任意分频比。
The double modulus divider structure with 12 stages cascade and feedback was adopted to realize any dividing ratio equal to or less than 8191.
电路采用12级级联反馈的双模分频器结构，可以实现小于或等于8 191分频的任意分频比。
The double modulus divider structure with 12 stages cascade and feedback was adopted to realize any dividing ratio equal to or less than 8191.
应用推荐