研究了用位总线微机构成的液压阀控马达速度闭环数字控制系统。
This paper deals with a closed-loop digital control for a hydraulic valve, controlled motor speed system.
详细描述了系统的特点和要求、分级分布式系统结构和以位总线为基础的数据通信网络。
The characteristic and requirement of the system, the distributed system structure and the data communication network which is based on the bit bus are described in detail.
SCSI-2标准出现于 1985 年，它的出现使数据速率更快（10MHz），总线也更宽（16位）。
The SCSI-2 standard began in 1985 and resulted in a faster data rate (10MHz) and a wider bus (16 bits).
尽管64位处理器通常都具有足够的数据总线来保证一切运行良好，不过在需要切换成64位数据时，要移动的数据大小依然是双倍的。
Although 64-bit processors typically have wide enough data busses to keep up fairly well, there's still a twofold increase in data to be moved when you switch to 64-bit data.
增加的数据总线带宽实现了对32位架构上通常可用的4gb以上可寻址内存空间的支持。
The increased data bus width enables support for addressable memory space above the 4gb generally available on 32bit architectures.
增强的总写架构-目前64位芯片上的总线架构比前几代更加的快也更加的广。
Enhanced bus architecture - The bus architecture on current 64-bit chipsets is faster and wider than earlier generations.
64位CPU拥有更宽的数据总线，但是同样是这个64位CPU可以运行32位的代码，而且拥有同样宽的数据总线。
A 64bit CPU will have a wide data bus, but recall that this same 64bit CPU can run 32bit code as well and it still has the big wide data bus to move things around with.
总线是一个代表位的数据和指令的途径。
A bus is a pathway for bits representing data and instructions.
强大，灵活的5立体声总线，24位数字的影响引擎提供了广泛的时间，频率和动态的影响以及影响链接。
Powerful, flexible 5-stereo bus, 24-bit digital effects engine offering a wide range of time, frequency and dynamic based effects as well as effects chaining.
文中论述4位数据总线点阵式液晶显示器LCD与低功耗单片微处理器80c31的硬件、软件接口方法和应用实例。
The hardware and software interface between 4-bit data bus dot matrix LCD and 80c31 microprocessor is described in this paper.
我们在单片FPGA中完成了6个端口、32位数据总线宽度交叉开关的设计。
We complete the design of crossbar switch with 6 ports and 32 bits data bus on one chip of FPGA.
利用位长度因素，本文推导了令牌总线和令牌环的简单吞吐性能模型。
By means of the bit length factor, the simple data throughput models of the Token Bus and Ring are derived.
串行推入总线125可以不宽于10位并且以较低的采样率运行。
The serial push bus 125 May not be more than 10 bits wide and runs a low sampling rate.
我们还推出了高达上千位的自动总线命令。
We've also introduced an automatic bus command up to thousands of bits.
探讨了CAN总线技术中位时间选定的技巧，并以实例说明了CAN总线中断接收的处理方法。
This paper discusses the skill of selecting bit times in CAN bus technology then shows how to deal with interrupt receiving with a concrete example.
本文从实用的角度详细介绍了参数的选择、位速率与传输距离的关系以及决定位速率的两个总线定时器值的计算。
This article presents the selecting of parameter, the relationship between bit rate and distance and the way of ascertaining the value of bit time register(BTR) in detail.
本文探讨了一种基于64位PCI总线的高速数据采集与存储系统的设计与实现方法。
This paper discusses the design and implementation methods of a high-speed data acquisition and storage system based on 64-bit PCI bus.
对微控制器而言，PDIUSBD12看起来就像一个带8位数据总线和一个地址位（占用两个位置）的存储器件。
To a micro-controller, the PDIUSBD12 appears as a memory device 8-bit data bus and 1 address bit (occupying 2 locations).
以此方法为基础，对基于485 -CAN总线的液位测量系统的硬件和软件设计做了详细的介绍。
Based on this method, the hardware and software of the liquid level measuring system based on 485-can bus are introduced in detail.
数据传送操作是通过CRC编码来保护的，因此，由拔插卡引起的任何位的变动将会被SD总线管理器侦测到。
Data transfer operations are protected by CRC codes; therefore, any bit changes induced by card insertion and removal can be detected by the SD bus master.
本文主要是基于RS485总线和CAN总线，研究总线技术在三种不同液位检测方法中的应用。
Based on the RS485 and CAN bus, research of their application in three different liquid level detection methods are conducted in this article.
论文介绍了多功能总线控制器编码器的设计，编码器有六个模块组成，分别为位控制单元、FIFO单元、帧分界符单元、数据转换单元、CRC校验单元和曼彻斯特编码单元。
The paper describes the design of encoder which is divided into seven modules: bit control unit, FIFO unit, frame delimiter unit, data conversion unit, CRC unit, Manchester encoding unit.
通过使用一个8位的单芯片和PCI总线结构，硬件加密卡的设计，这是直接插在总线。
By using a 8-bit single-chip and a PCI bus structure, a hardware encryption card was devised, which was directly inserted in the bus.
各个节点设计上采用内置CAN模块的飞思卡尔16位单片机作为主控芯片来搭建硬件电路，以实现CAN总线的物理层和数据链路层。
Through using 16-bit freescale MCU embedded CAN controller as master chip in each node, it achieved the design of hardware circuit, so realized CAN physical layer and CAN data link layer.
各个节点设计上采用内置CAN模块的飞思卡尔16位单片机作为主控芯片来搭建硬件电路，以实现CAN总线的物理层和数据链路层。
Through using 16-bit freescale MCU embedded CAN controller as master chip in each node, it achieved the design of hardware circuit, so realized CAN physical layer and CAN data link layer.
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