位同步化状态错误的具体信息。
它本身不含有位同步时钟分量。
位同步电路在现代通信中占有重要地位。
Bit synchronizing circuits are very important in modern communication.
本文主要以一阶环为例讨论位同步信号提取。
This paper discusses extraction of the bit-synchronous signal with a first-order ADPLL mainly.
导航电文提取中最重要的步骤是位同步和帧同步。
The most important steps for navigation data extraction are bit synchronization and frame synchronization.
对于非相干解调本文提出了一种快速位同步算法。
A rapid symbol timing scheme is proposed in this paper based on noncoherent demodulation.
码元定时恢复(位同步)技术是数字通信中的关键技术。
Symbol timing recovery (Bit Synchronization) is the key technology in the digital communication.
测试结果显示，位同步抖动范围小于符号周期的8%。
The test result shows that the dither range is less than 8% of the symbol period.
位同步检测是实现全数字接收机开环定时恢复的关键技术。
The bit synchronization detect is very important in opened loop timing recovery of all digital receivers.
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
经过线路编码，可以使基带信号含有定时信息，解决了通信中的位同步。
The line code is an efficient way to make the baseband digital signal have some massage about the bit synchronization.
本系统利用集成时钟和数据恢复芯片SY87700L实现了可靠的位同步。
This system select integrate chip SY87700L to realize bit synchronizing reliably .
在中低速散射通信中，调制解调器的位同步信号通常从含有同步信息的包络中提取。
In the troposcatter communication at low rate or medium rate, a bit synchronization used by modem is usually extracted from the envelope that contains synchronization information.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
USB的电气特性反映了端口驱动电路、传输电平、编码结构、位同步处理及供电方式。
The USB electrical specifications describe the port driver circuit, electrical level of data transmission, code structure, bit synchronization and power distribution.
在接收端主要研究了频差校准、位同步和均衡等关键技术，其中重点放在了均衡技术上。
On the receiving end, mainly studies the key technologies of Calibration frequency difference, Synchronization and adaptive equalization, of which adaptive equalization has been emphasized the most.
针对短时突发数据接收对位同步电路的要求，设计一种基于FPGA的硬件开环位同步电路。
A hardware electrocircuit scheme for bit synchronization are designed to met the demands of bit synchronization little paroxysmal data receiving in wireless digital system.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
本文根据突发式数字通信快速锁相要求，提出一种位同步信号提取的新的快速全数字锁相环方案。
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.
为了实现GMSK信号解调，接收机中dsp实现了调制信号的误差频谱估计、位同步恢复及译码。
To demodulate GMSK signal, DSP is used in receiver to achieve error spectrum estimation, bit synchronization recovery and decode.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
位同步信号本身的抖动、错位会直接降低通信设备的抗干扰性能，使误码率上升，甚至会使传输遭到完全破坏。
Jitter and misplace of the bit synchronization signal will reduce the anti-interference performances of communication equipment directly, also increase bit error probabaility.
HDL是设计数字逻辑电路必不可少的通用工具，该文给出了位同步性能较好的积分型自同步的一个HDL实现。
HDL is an essential general tool in digital logical circuit design. A HDL implementation of the integral bit synchronization with good performance is provided.
首先将接收到的PCM数据流进行位同步，然后经过一双口ram作为缓冲，直接送入微机进行实时帧同步码粗同步。
PCM stream which has been bit blocked is sent into computer, buffered by a dual port static ram, then it's frame blocked roughly.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
经过限带滤波后的QDPS K信号的码元波形可分为稳定区与过渡区，根据这一特点可以利用DFT方法来实现信号的解调和位同步。
After a bandpass filter, QDPSK signal's symbol can be divided into steady section and transition section, so the demodulation and synchronization for the signal can be realized with DFT.
另一种避免同步问题的方法是，分配一个很大的全局内存块，并将其划分为较小的槽位，其中每个槽位都可由一个线程用来进行日志记录。
Another way to avoid synchronization issues is to allocate a large chunk of global memory and break it into smaller slots, where each slot is to be used by one thread for logging.
质子同步加速器，建于1957年位于杜布纳的加速器，是当时最庞大和最强大的加速器。
Synchrophasotron, an accelerator built in Dubna in 1957, has become the biggest and the most powerful for his time.
如果将所有信息放在同一位置，就会减少信息失去同步的可能性。
If you put all that information in one place, you cut down on the potential for information falling out of sync.
在以理想的位周期的百分数表示的同步数据里，用以表示两个峰值间的最大定时变化值。
The maximum peak-to-peak value of the timing variations in synchronous data expressed as a percentage of the ideal bit period.
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