实际运行表明：该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点；
Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability.
阐述了用硬件描述语言设计仲裁逻辑的具体过程，给出了逻辑状态机和转换关系。
The design procedure of arbiter logic by hardware description language and state with transform conditions are also demonstrated.
改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
现在用户可以通过ESB访问这些服务，ESB查询ServiceRegistry并根据仲裁逻辑将请求重定向到适当的服务。
Users now access services via an ESB, which queries Service Registry and redirects requests to the appropriate services based on mediation logic.
描述了CMMS系统结构及总线仲裁链式环逻辑，介绍了通信软件设计思想，并给出了发送和接收程序流程图。
The architecture and logic of chained arbitration-bus, the design idea of communication software, and the diagrams about transmitting and receiving are given.
本文介绍了一种总线仲裁器的逻辑电路。
In this article the design of a cost-effective bus arbiter is discussed.
逻辑是具体案例的法官和仲裁者。
Logic is the common judge and arbiter of all particular investigations.
逻辑是具体案例的法官和仲裁者。
Logic is the common judge and arbiter of all particular investigations.
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