讨论了简化的四象限乘法器的原理。
The principle of simplified four-quadrant multiplier was discussed.
提出了一种快速有限域乘法器结构。
实践表明，这是一种实用的数字乘法器。
本文简要介绍了几种结构的数字乘法器。
This paper presents briefly the digital multiplier with different structure.
图24给出了一个简单的模拟乘法器电路。
A simple embodiment of the analog multiplier is shown in Figure 24.
本文给出一种新型四象限模拟乘法器的实现电路。
In this paper, a new type of reality circuit of four quadrant analogue multiplier is presented.
建立了最新的高性能模拟乘法器ad734模型。
A behavioral model for the newest high performance multiplier AD734 is described.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
与传统的移位乘法器相比，它将乘法器速度提高一倍。
Compared with the traditional serial multiplier, it can obtain twice speed-up.
本文给出了二进制补码和无符号乘法器的通用表达式。
The uniform expression of multiplier of two's complement and unsignednumber are given in this paper.
本文给出一种任意多位的保留进位阵列乘法器的自动设计方法。
This paper presents an automatic design method for a carry save array multiplier with arbitrary number of bits.
复合晶体管，复合晶体管对，电流平方器和CMOS模拟乘法器。
Composite transistor, composite-transistor pair, current squarer, and CMOS analog multiplier.
乘法器将所述减法结果乘以十六进制数‘10’，产生第一临时变量；
The multiplier multiply said results with 10 of hexadecimal to produce No. 1 variable.
提出了一类新的具有高度规则性的部分并行三项式有限域乘法器架构。
A new high regular structure of partial parallel multiplier for irreducible trinomial generated finite field is proposed.
本文给出一种新型四象限模拟乘法器(4 - QAM)的实现电路。
A switched-capacitor SO four quadrant analog multiplier 4-qam is presented in this paper.
根据平行并行乘法器，设计了适用于模乘运算的一维阵列组合乘法器。
The one-array combinative multiplication was designed on the basis of the parallel multiplication.
本论文研究的主要内容是有限域算术、椭圆曲线加密算法和有限域乘法器。
The finite field arithmetic, elliptic curve cryptography (ECC) and the finite field multiplier are investigated in this thesis.
着重讨论了以大规模集成电路为基础的并发结构数字乘法器的设计和性能。
The design and performance of multiplier with concurrent structure based on large scale integrated circuits technique are discussed in detail.
乘法器是数字信号处理和媒体处理中应用最多，硬件面积最大的执行部件。
Multiplier is one of the most important units used in DSP and multimedia data processing.
讨论了基于MOS晶体管亚阈值区特性的CMOS四象限模拟乘法器的设计。
The design technique for a CMOS four quadrant analog multiplier is presented, which is based on the characteristics of the MOSFET subthreshold region.
利用两次回转方法，由运算跨导放大器（简称OTA）构成浮地电容乘法器。
Using the approach of twice impedance inversion, a floating capacitance multiplier was built by operational transconductance amplifier (OTA).
提出了一种基于IEEE754标准的双精度浮点乘法器的流水线设计方法。
A new design method of pipelined multiplier for double precision floating point data based on IEEE754 standard was proposed.
在深入探讨调制波的产生原理基础上，设计了一个基于乘法器的调制波发生电路。
The generation of modulation wave by wide band multiplier is designed after deep discussion on theory of the modulation wave generation.
提出一种采用模拟乘法器和模拟积分器作为基本元件构成功率方向继电器的方案。
A project to design a power direction relay, which is based on an analog multiplier and an analog integrator, is presented in this paper.
设计完成的乘法器只产生9个部分积，有效降低了部分积压缩阵列的规模与延时。
The designed multiplier has only 9 partial products, which effectively reduces the size and delay of compression array.
此压缩器已作为一个压缩模块，用在32位浮点乘法器的软核设计中，得到了很好的结果。
The compressor has been used in the IP software core design of 32bits floating multiplier as a module, and acquire a good result.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
给出了系统硬件结构，对以内部硬件乘法器为FFT处理核的谐波分析技术进行了详细分析。
The harmonic analysis with the FFT processing nucleus based on the internal hardware multiplier is analyzed in detail.
利用偏差分析的结果，可以得出一个对正态过程和随机相位正弦波都是无偏的不用乘法器的相关器。
Taking advantage of the analysis of the bias, an unbiased correlator without multiplier is deduced for Gaussian process and sinusoidal wave with random phase.
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