分析了空气簇射阵列触发计数率的气象效应；
The meteorological influences on trigger rate of ASA are analysed.
设计了双边沿触发计数器，并利用电路的冗余特性，降低了系统的功耗。
A double edge triggered counter is designed, and the redundancy attribute of the circuit is utilized to decrease the power consumption of the system.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
向数据库添加触发器，以便对该表中的记录的每个更新都会导致修订计数器递增。
We add a trigger to database so that every update to a record in the table increments the revision counter.
如果发生了衰变，那么会触发一个连接在盖革计数器上的锤子，打碎瓶子，释放毒气，杀死猫。
If it does, then a hammer connected to a Geiger counter will trigger, break the vial, release the poison, and kill the cat.
当该探针触发时，您希望计算调用的次数，并发送这个计数以及表示调用进程ID（PID）的信息。
When this probe fires, you want to count the number of invocations and emit this count with an indication of the calling process ID (PID).
BusinessMeasure模型允许为流程定义性能指标、计数器、秒表和触发器，并使用其进一步定义KPI。
The Business Measure model allows you to define performance metrics, counters, stopwatches, and triggers for a process, and use them to further define KPIs.
盖革计数器(Geiger counter)被用来测量原子衰变时的放射线，如果原子发生衰变，盖革计数器将会触发氰化物气体的释放，致猫于死地。
Geiger counter was included to measure radiation if at some point an atom decayed. Should that happen, the Geiger counter would trigger the release of cyanide gas, which would kill the cat.
盖革计数器(Geigercounter)被用来测量原子衰变时的放射线，如果原子发生衰变，盖革计数器将会触发氰化物气体的释放，致猫于死地。
A Geiger counter was included to measure radiation if at some point an atom decayed. Should that happen, the Geiger counter would trigger the release of cyanide gas, which would kill the cat.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
由89c52和8254组成数据处理电路。外部测量信号以外部中断方式触发89c52读取8254计数。
The data acquisition circuit is composed of chip 89C52 and 8254. External measuring signal at interrupt mode triggers 89c52 to read number in 8254 counter.
本文是关于采用三个TTLD触发器和六个译码器来组成扭形计数器的设计。
This paper is concerned with three TTL D flip-flops and six Decoders which are buith by Ring counter design.
数据采集系统触发电路、随机采样短时间产生电路、存储器地址计数器电路等相关控制电路的设计、仿真和调试；
The circuits revelent to data acquisition system such as trigger circuit, the circuit of short time generator in random sampling etc, are designed, simulated and adjusted.
数据选择器则将两个计数器中处于保持状态的奇偶数据交替输出，实现双边沿触发加法计数器的功能。
Data selector alternately to realize the functions of double edge trigger addition counter output the odd and even data in two counters.
说明：定时上传下载FTP，定时统计数据，定时入库并通过存储过程触发数据。
From time to time to upload and download FTP, timing statistics, regular storage and trigger data through stored procedures.
此脉冲信号还是行计数器的触发信号，间接地控制振镜场扫的正程和逆程。
The horizontal line's counter is also activated by this signal to control galvanometer up and down.
此外，还提出了使用附加触发器时循环码计数器的快速综合法。
Furthermore, a fast synthesis for the cyclic-code counter using additional flip-flop is also proposed.
提出用纯二值结构的三值T触发器和普通的二值触发器一起构造混值N进制计数器的设计方案。
This paper proposes the design method of a mixedvalued modulo-N synchronous counter by using both common binary flip-flops and ternary T flip-flops which has binary structure.
最后用计算机模拟程序检验绝热触发器和可变计数电路的结果。
Finally, Computer simulation has shown that above flip-flop and adiabatic variable counter are stable with lower power consumption.
而副本的分配是动态的，其处理准则是根据系统的访问统计数据，触发对系统副本的添加或者是减少，或者是副本的迁移，从而达到最佳的负载平衡。
To obtain best load balance, the copies assignment is dynamic and according to system statistics data to trigger copies increasing or reducing, and perhaps copies migrating.
该装置用真有效值电路检测非正弦焊接电流值，用中断和定时计数器实现了可控硅的精确触发。
The measuring circuit for RMS of non-Sin welding current and the precise triggers of SCR using interrupt controllers and timers in AduC812 MCU are also described.
原始条件：使用D触发器（ 74LS 74 ）、“与”门 （ 74 LS08 ）、“或”门（ 74 LS32 ）、非门 （ 74 LS04 ），设计三位二进制模5计数器。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
原始条件：使用D触发器（ 74LS 74 ）、“与”门 （ 74 LS08 ）、“或”门（ 74 LS32 ）、非门 （ 74 LS04 ），设计三位二进制模5计数器。
Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
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