这是在一个时钟周期内必须完成的操作数量。
This is the number of operations that must be completed in a single cycle of clock time.
一个处理器的时钟周期内，没有发生。
时钟周期数-用于CPU绑定的问题。
加快时钟周期。
延时——一条指令用来产生最终值所使用的时钟周期数。
Latency — The number of clock cycles an instruction USES to produce a final value.
每个解码输出在一个全时钟周期内保持高电平。
控制器需要很多时钟周期才能完成移位的过程。
这种时钟周期以每两年发生一次突变的速度为基准。
The clock ticks at a rate of about one mutation every two years.
暂停（Stall） ——处理器不开始执行新指令处的时钟周期。
Stall -- A clock cycle where the processor does not begin a new instruction.
SPU本身使用向量操作，每个时钟周期可以执行多达8条浮点指令。
An SPU USES vector operations itself and can thereby execute up to eight floating point instructions per clock cycle.
这个游戏在快速的硬件上不会有问题，但你会浪费不少贵重的时钟周期。
The game will have no problems on fast hardware, but you are wasting so many precious clock cycles.
由于双时钟的ALU， 因此在P4 上可能有半个时钟周期。
On P4 half cycles are possible due to the double-clocked ALU.
垂直组表明在一段时间内（多个时钟周期期间）利用了三个执行单位。
The vertical sets indicate the utilization of the three execution units over time (during multiple clock cycles).
设计方案的优劣依赖于精确到时钟周期级别的微体系结构模拟器评估。
To evaluate the design alternatives, Micro-architects rely on the cycle level micro-architecture simulators.
一个操作系统典型地由一个函数调用集、软件中断和定期时钟周期组成。
An operating system typically consists of a set of function calls, or software interrupts, and a periodic clock tick.
一个好的经验法则是在32位CPU上以每字节10个CPU时钟周期的速率加密。
A good rule of thumb is to encrypt on a 32-bit CPU at the rate of 10 CPU clock cycles per byte.
变量声明在很多情况下花费时钟周期，你可以结束这种没有价值的浪费。
Since declarations of variables in many cases costs computational cycles, you may end up wasting time for nothing.
设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。
It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
指令4可以在指令3之后紧接的那个时钟周期执行，因为它不需要指令3的结果来执行。
Instruction 4 can be issued in the clock cycle immediately after instruction 3 because it does not require the result of instruction 3 to execute. You can visualize it like this.
除了处理器时钟速度外，另一个重要的处理器性能度量是每条指令的时钟周期(CPI)。
In addition to processor clock speed, another important processor performance metric is clock cycles per instruction (CPI).
同时多线程处理器在每时钟周期从多个线程读取指令执行，极大地提高了指令吞吐率。
Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle.
摘要：随着数字系统的工作频率的不断提高，时钟周期逐渐变小，而系统时序却越来越复杂。
Absrtact: Along with the increase of digital system working frequency, clock period gets shorter, timing of the system becomes more complex.
它以CCD读出时钟周期为单位调节曝光时间，提高了系统的响应速度和对外界的适应能力。
The method takes the CCD read clock as the unit to adjust the exposure time. It improves the system's responsiveness and ability to adapt to the outside world.
每个处理器内每组三个水平方框显示了在指定的时钟周期内，三个执行单位是如何被使用的。
Each set of three horizontal boxes within each processor shows how the three execution units are being used during a given clock cycle.
不过对于现在来说，我们将简单地展示如何通过调整selb和stqd指令的顺序来节省两个时钟周期。
However, for now, I will simply show how to save two clock cycles by adjusting the order of the selb and STQD instructions. Here is the new order.
Devadas已经成功演示了一种能计算带宽分配且能在一个时钟周期内改变连接传输方向的小型电路。
Devadas has demonstrated that small circuits connected to the cores can calculate the allotment of bandwidth and switch the direction of the connections in a single clock cycle.
POWER 4微处理器每个时钟周期收集一组指令(最多有5个)，并在每个时钟周期内完成一组指令。
The POWER4 microprocessor collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
CL是指“CAS延迟”，是指收到命令以后，再数据开始传输以前，所需要的时钟周期的数量。
Cl stands for "CAS latency," which is the number of clock cycles it takes before data starts to flow once a command is received.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
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