• 这个脚本使用谓词区分最终结果为素数和非素数的计算,把从start探测到done探测的时间数据累加起来。

    This script aggregates the timing data from the start probe to the done probe, using a predicate to identify whether the calculation was ultimately for a prime or non-prime number.

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  • 所有数据库累加,通过了超过1TB的信息。

    We counted all the databases up and it passed 1 TB of available data.

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  • 瑞信经济学家警告称,美国劳工统计局(BureauofLaborStatistics)建议要谨慎累加各州的就业数据。

    The Bureau of Labor Statistics suggests caution in doing a 'sum-of-states series,' the Credit Suisse economists warn.

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  • 我们还使用了一个命名参数来将关联数据和样本一起传递给累加器集。

    We also use a named parameter to pass covariate data into the accumulator set along with the samples.

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  • 为了解决多层的少样本或无规则数据的建模问题,在一般多层统计模型的基础上提出了多变量整体模式的累加多层统计模型。

    For modeling the multilevel few sample or irregular data, the accumulated multilevel statistical models of multivariate full model was built on ordinary multilevel statistical models.

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  • 累加器集每次接受一个数据样本,并将它们按顺序传播给每个累加器。

    An accumulator set accepts samples one datum at a time, propagating them to each accumulator in order.

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  • CPU有一个累加寄存器用于临时存储数据。

    The CPU contains an accumulator (ac) to temporarily store data.

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  • 运算器:运算器是数据加工处理部件,它是由算术逻辑单元(alu)、累加器、数据缓冲器等组成。

    Arithmetic unit: arithmetic unit is a data processing unit that consists of arithmetic logic unit (ALU), accumulator, data buffer, ect.

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  • 针对GIS面状拓扑数据,提出了一种快速栅格化算法———差分边界标志与累加扫描算法。

    Aiming to rasterize topological region data in GIS, we present a fast algorithm named as difference boundary-labeling and accumulating-scan algorithm.

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  • 介绍了中国VLBI网FX型相关处理机的结构和功能,并着重阐述了相关处理机的长期累加器子系统(LTA),它是相关处理机的条纹数据压缩部件。

    The structure and the functions of the high-speed FX correlator of Chinese VLBI network are described, and its long term accumulator (LTA) is introduced in detail.

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  • 采用加权方法生成新的数据进行累加建模,并在求解过程中改变初始条件。

    The model was built by using data accumulation with weighted method and changing the initial conditions in calculating process.

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  • 本发明无需用户使用其它的计算工具手动计算,方便地实现了用户对网页页面表格数据的累加。

    The user can manually make calculation without using other computing tools, thereby facilitating the user to accumulate the web page table data.

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  • 该技术通过累加全部边界的数据,而不是仅仅两个点来提高这些测量的准确性,它也有节省时间和去除操作者主观倾向的特点。

    The technique adds greatly to the accuracy of the measurement by accumulating data over the entire boundary rather than just two cuts.

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  • 本发明能够根据用户的选择,自动将用户想要进行累加的数据进行累加,并将结果显示给用户。

    The invention can automatically accumulate the data required to be accumulated by the user based on the selection of the user, and displays the result to the user.

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  • 每来一个时钟脉冲,N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加,并将结果送相位寄存器输入端。

    Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.

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  • 文章提出的结构以50%的额外硬件资源,实现基于循环累加的传统DA结构8倍的数据处理速度。

    The proposed architecture achieves 8 times throughput rate of conventional DA based on shift-add with 50% extra hardware cost.

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  • 将GM(1,1)模型与随机数据的累加生成相结合,对未来异常降水发生时刻作预测。

    It is shown that by combining GM (1, 1) with the addition generation of random Numbers, can be employed to predicts the time of forthcoming abnormal seasonal precipitation.

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  • 因此,在信号处理期间对时间要求严格 的响应仅仅限于当前对数据字进行处理的累加器级。

    As a result, a time-critical response during signal processing is limited just to the accumulator stage which is currently processing the data word.

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  • 在精确重建滤波过程中,需要计算投影数据的雷当变换,本文采用普通累加法和辛普森直线积分法来完成对象素网格的采样。

    The Radon transform of the projection is calculated in the filtered process of exact reconstruction, Siddon and Simpson integral are used to sample the pixels to get the projection.

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  • 文章提出的新型乘法累加器,具有在不同模式下分别处理16位与32位数据,或16位与32位数据混合运算能力。

    The multiply-accumulate unit (MAC) specified in this paper describes a novel architecture. It can handle operation of 16-bit and 32-bit separately or mixed operation of them in different modes.

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  • 文章提出的新型乘法累加器,具有在不同模式下分别处理16位与32位数据,或16位与32位数据混合运算能力。

    The multiply-accumulate unit (MAC) specified in this paper describes a novel architecture. It can handle operation of 16-bit and 32-bit separately or mixed operation of them in different modes.

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