清单29中的另一个例子显示一个数字时钟。
电视台会把数字时钟嵌入在屏幕上。
墙上的数字时钟显示着阿富汗和伊拉克的两地时间。
A digital clock on the wall shows the time in Afghanistan and Iraq.
那是数字时钟的零件。
xclock数字时钟仍然出现在桌面上，但它已经停止运行。
The clock is still on your desktop, but it has stopped running. Suspending it did exactly that.
佩带者在其手腕划一个圈，该设备便会映射出一个数字时钟盘面。
The wearer can draw a circle on his or her wrist and the device will project a digital clock face.
大规模集成电路晶元是中等到大规模的记忆晶元，用于8位处理器、数字时钟和计算器。
Lsi chips are medium to large size memory chips, 8 bit microprocessors, digital clocks or calculators.
大部这些命令的运行都很快，但现在假设您运行的是图形化桌面，并且想在桌面上显示一个数字时钟。
Most such commands run quickly, but suppose you are running a graphical desktop and would like a digital clock displayed on the desktop.
设计师马腾·巴斯编成1美刀iPhone应用程序的实时模拟数字时钟，本来是一个博物馆的作品。
Designer Maarten Baas adapted his Real Time Analog Digital Clock, originally a museum piece, into a one dollar iPhone app.
结合嵌入式系统课程的特点，并以数字时钟的设计为例，介绍了将建构主义教学理论应用于嵌入式系统课程教学。
Combining the Constructivism Ideology and taking the case of digital clock design, this paper presents the Application of Constructivism Ideology in Embedded System course teaching.
据《华尔街日报》报道，挪威广播公司正策划一档24小时的直播慢节目，记录建筑工人如何使用木头制作数字时钟。
According gto the Wall Street Journal, NRK is also considering a 24-hour live feed of construction workers building a digital clock out of wood.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
本设计基于单片机技术原理，以单片机芯片AT89C51作为核心控制器，通过硬件电路的制作以及软件程序的编制，设计制作出一个多功能数字时钟系统。
This text is mainly to introduce a method of making the multi-functional digital clock with Single-Chip Microcomputer AT89C51 as the center controller.
竞争者将面对成千上万的表面上随机的数字和字母，还有一个倒计时时钟。
Competitors are then faced with a grid of apparently random Numbers and letters along with a countdown clock.
这座高6.5米，宽5米的数字显示式时钟由钢材料制成，一刹那停止在奥运倒计时第500天7小时6分56秒。
The steel digital clock measuring 6.5 metres tall and five metres long froze with 500 days, 7 hours, 6 minutes and 56 seconds to go before the start of the Games.
你可以改变数字的颜色和实际显示的信息，但在外观方面，这款应用程序保持着一个简单的时钟样式。
You can change the color of the numerals and what info is actually displayed, but as far as looks go, this app keeps it clock-like and simple.
固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。
Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.
网同步技术是数字通信系统的关键技术之一，网同步时钟是网同步技术的关键设备。
The network synchronization is one of the key technologies for digital communication and the clock is the most important equipment in the network synchronization.
这是一个多语种的发言时钟使用超过50种不同的皮肤，以显示时间，您使用的不是数字或模拟显示器。
This is a multilingual Speaking Clock that uses over 50 different skins to show the time to you using either digital or analogue displays.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
用复杂可编程芯片(CPLD)实现，并用于雷达数字光纤通信系统的信道编码，提高了时钟提取的性能。
The scheme can be implemented by using the CPLD chip, and used for the channel coder in a radar digital optic-fiber communication system and improving the features of clock extraction.
在这种趋势下，时钟的数字化、多功能化已经成为现代时钟生产研究的主导设计方向。
In this trend, digital clock, multifunction clock has become the modern design of the production of research-led direction.
该方法是一种基于信号采样时钟速率的全数字化处理过程，其同步精度可达到信号采样间隔的1%以上，且便于FPGA或DSP实现。
The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
发射和接收单元(5)与时钟同步地将接收模拟基带信号转换为接收数字基带信号。
The transmitting and receiving unit (5) converts the reception analog baseband signal into a reception digital baseband signal in synchronization with a clock.
时钟同步是数字设备协调无误运行的前提条件。
Clock synchronization is the precondition for digital equipment to work in harmoniously.
发射和接收单元(5)与时钟同步地将发射数字基带信号转换为发射模拟基带信号。
The transmitting and receiving unit (5) converts the transmission digital baseband signal into a transmission analog baseband signal in synchronization with the clock.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
在具体的电路设计中，主要研究设计了一个开关电容比较器、一个两级运算放大器、数字校正电路和一个时钟提升电路。
For circuits design, the thesis designs a switch capacitor comparator circuit, a two stage amplifier, a digital correction circuit and a clock pump-up circuit.
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