变频调速系统主电路采用交-直-交形式，以可编程逻辑器件(CPLD)作为调速系统逆变电路功率开关器件IGBT的逻辑控制器件。
Alternating-direct-alternating circuit is adopted and CPLD is used as logic control device of power IGBT in main circuit of variance-frequency timing system.
本系统采用了以DSP、MCU（微控制器）、CPLD（复杂可编程逻辑器件）为核心的系统硬件结构以及数字视频技术。
The system uses DSP, MCU (Microcontrol Unit) and CPLD (Complex Programable Logic Device) as the core of the system hardware and uses digital video technology.
根据单元级联多电平变换器拓扑结构及其脉宽调制技术的特点，以数字信号处理器和复杂可编程逻辑器件为核心，设计了多电平变换器的控制器。
On the basis of topology of cascaded multilevel convertor and its PWM technique, designed the controller of multilevel convertor at the core of DSP and CPLD.
其中现场端的设计以单片机技术为核心，控制器端的实现以可编程逻辑器件设计技术为核心。
In the field unit the core is Singlechip, and in the central controller is Programmable Logic Device.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
利用嵌入式ARM微处理器LPC 2292和可编程逻辑器件EPF10 K 10为主要控制器件来完成LED显示屏设计。
The paper utilizes embedded ARM microprocessor LPC2292 and programmable logic device EPF10K10 as the device mainly to come to finish LED display screen design.
介绍了总线控制器pci9054的桥式作用、用可编程逻辑器件模拟LOCAL总线侧cpu的设计、EEPROM的配置以及总线的数据传输操作过程，然后在此基础上给出了数据采集系统的设计。
It includes that the bus controller PCI9054 action, the simulation of the CPU design with CPLD on the LOCAL bus side, configuration of EEPROM and the bus operation of the data transmission.
介绍了总线控制器pci9054的桥式作用、用可编程逻辑器件模拟LOCAL总线侧cpu的设计、EEPROM的配置以及总线的数据传输操作过程，然后在此基础上给出了数据采集系统的设计。
It includes that the bus controller PCI9054 action, the simulation of the CPU design with CPLD on the LOCAL bus side, configuration of EEPROM and the bus operation of the data transmission.
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