对互连寄生电容提取的研究背景进行了简要的介绍。
In this paper, the background of parasitic capacitance extraction of interconnects are briefly introduced.
介绍复杂互连寄生电容器的结构及对其实现虚拟多介质切割的方法。
In this paper, the complex 3D structures of VLSI interconnect capacitors and the virtual cutting method for them are presented.
通过分析互连几何参数波动与互连寄生参数的关系，得到其近似的函数关系表达式。
The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters.
随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。
The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.
在3dVL SI互连寄生电容的边界元素法计算中，多孔平面的边界元划分是十分困难的问题。
In the computations of 3d VLSI parasitic interconnect capacitance, it is very difficult to partition the boundary elements on a multi hole surface.
在3dVL SI互连寄生电容的边界元素法计算中，多孔平面的边界元划分是十分困难的问题。
In the computations of 3d VLSI parasitic interconnect capacitance, it is very difficult to partition the boundary elements on a multi hole surface.
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