在一个实施例中，集成到芯片组102上的系统存储控制器106对中央处理器100提供通过互连110对系统存储器子系统108的访问。
System memory controller 106, integrated on chipset 102 in one embodiment, provides central processor 100 access to the system memory subsystem 108 through interconnect 110.
互连410提供中央处理器400与芯片组408之间的通信链路。
Interconnect 410 provides a communication link between central processor 400 and chipset 408.
中央处理器302和图形处理器304通过互连308与芯片组306进行通信。
Central processor 302 and graphics processor 304 communicate with chipset 306 through interconnect 308.
在这个实施例中，系统存储控制器402集成到中央处理器400上，以便提供通过互连406对系统存储器404的访问。
In this embodiment, system memory controller 402 is integrated on the central processor 400 to provide access to system memory 404 through interconnect 406.
同样在另一个实施例中，存在设置于计算机系统中并耦合到互连406、410的多个中央处理器(在这个图中没有示出多个处理器)。
Again, in another embodiment, there are multiple central processors located in the computer system and coupled to interconnects 406 and 410 (multiple processors are not shown in this figure).
耦合到中央处理器100以及芯片组102的互连104用于这两个代理之间的通信。
Interconnect 104, coupled to both central processor 100 and chipset 102, is used for communication between these two agents.
耦合到中央处理器100以及芯片组102的互连104用于这两个代理之间的通信。
Interconnect 104, coupled to both central processor 100 and chipset 102, is used for communication between these two agents.
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