The WISHBONE bus is suitable for system communication on chip and configurable.
内部总线采用适合片上系统通信，高可配置性的WISHBONE总线。
The logic design and physical implementation of a GPIO_WB controller based on WISHBONE Bus are achieved.
完成了一种基于WISHBONE总线的GPIO_WB控制器的逻辑设计和物理实现。
This paper based on the mechanism of DDR-SDRAM, gave a way to construct a DDR-SDRAM controller based on WISHBONE bus protocol, and also introduced a forecast method to improve DDR's performance.
SDRAM是当今一种流行的高速存储器。通过和普通sdram存储器对比，阐述了WISHBONE总线协议下ddr存储器控制器的设计方法和注意事项，并提出一种提高DDR工作效率的预测机制。
The special difficulties lie in the implementation of the burst transmission of the AHB bus, and the supporting of the mutual access between multiple AHB and multiple WISHBONE.
该方法难点在于AHB总线突发传输白勺实现，且支持多个AHB设备和多个WISHBONE设备之间白勺互相访问。
The special difficulties lie in the implementation of the burst transmission of the AHB bus, and the supporting of the mutual access between multiple AHB and multiple WISHBONE.
该方法难点在于AHB总线突发传输白勺实现，且支持多个AHB设备和多个WISHBONE设备之间白勺互相访问。
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