In order to reduce the cost of developing VLSI test program and shorten developing cycle, an idea of a simulator design of test system and gives the simulators structure and function is put up.
为了降低开发超大规模集成电路器件的测试程序的费用，缩短开发周期，给出了一种设计和开发测试系统仿真器的基本思想、结构组成及其功能。
The access time is important for the system chip with high performance, the low power has been the spotlight and challenge in VLSI design.
高性能的系统芯片对数据存取速度有了更严格的要求，同时低功耗设计已成为VLSI的研究热点和挑战。
With the development of VLSI, many people consider of using the existing circuits to accelerate the design speed of the system, which is called design reuse.
超大规模集成电路的飞速发展，使人们越来越多的考虑利用已设计好的电路模块来加速系统设计，即设计重用问题。
A computer aided simulation system CASSY (computer aided simulation system) for VLSI (Very Large Scale Integrated) circuits systems was presented to keep the design procedure of VLSI out of mistakes.
为保证超大规模集成电路(VLSI)设计过程的正确无误，本文提供了一个电路系统的计算机辅助模拟系统(CASSY)。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems and lays a foundation for the design of the asynchronous VLSI system.
本论文在异步电路的基本原理和特点及异步vlsi系统的主要设计原理、方法和模块等方面展开了广泛的研究，为异步vlsi系统的设计奠定了基础。
According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.
论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。
The method utilizes the estimation of time-related power consumption of the signal in the VLSI circuit and system design to conquer the restriction of the prior method.
本发明方法能够在VLSI电路和系统设计中，信号在时间上相关性 时的估计功耗，克服了原有方法的局限性。
The problem on the shortest connection in the plane is used widely, such as the transportations, the construction of road system, the design of VLSI, etc.
平面上的最短连线问题在交通运输、道路建设、VLSI设计中有广泛的应用。
As the scale of digital circuits become very bigger and the function of circuit become very complicated recently, it is difficult to ensure the correctness of design in VLSI system.
近年来，由于电路规模不断增大和电路功能日趋复杂，使得大规模集成电路的设计很难保证逻辑设计的正确无误。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
So the efficient verification of the design and implement of circuit must be introduced for building the higher responsible VLSI system.
为了设计和建立高可靠性的VLSI系统，必须对VLSI的设计和实现进行有效的验证。
应用推荐