This paper proposes a VLSI architecture of multilevel filter.
提出了一种多级滤波器的VLSI硬件实现结构。
His research interests include image processing, video coding, VLSI architecture.
主要研究图像处理，视频压缩，VLSI结构。
The VLSI architecture is regular, and video signal processing speed is very high, because of the regularity of the proposed algorithm.
算法的规则性决定了对应的VLSI结构的规则性、紧凑性和视频信号处理的高速度。
A video interpolation algorithm based on triangulation analysis and high-frequency compensation is proposed. And its VLSI architecture implementation is given in this.
提出一种基于三角分析和高频补偿的视频插值算法及其VLSI实现方法。
In this paper, a VLSI architecture for channel estimation and cyclic restoration in TDS-OFDM is proposed. The realization of cyclic correlation introduced is high-speed and low-cost.
针对TDS - OFDM系统的信道估计与数据循环化算法提出了一种硬件实现架构，其中循环相关的实现架构速度快且节省硬件资源。
According to the research on the existing VLSI architecture of the bit-plane coding, a new VLSI architecture is proposed in which stripe-column and coding are both implemented in parallel.
研究了现有的位平面编码VLSI结构，设计了一种条带列与编码通道全并行的VLSI结构，解决了内部存储资源占用率高的问题。
Through the research of VLSI architecture of fast codewords search algorithms, we can provide a foundation for the implementation of detailed and sophisticated image coding schemes in the future.
通过对矢量量化快速码字搜索算法的VLSI结构的研究，为进一步设计更为详细和复杂的图象编码系统提供基础。
It is a very high speed VLSI Design through the pipeline architecture with power optimization.
该设计采用流水线处理结构，能达到非常快的处理速度，同时进行了功耗优化。
Based on the full use of parallel architecture, an efficient solution for VLSI implementation is described.
在采用并行结构的基础上，给出了一种高效的VLSI实现方案。
In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation.
提出了比特平面并行处理的零树编码结构。
To achieve real-time 3-D medical image despeckling, a novel fast algorithm and high-performance Very Large Scale Integrated (VLSI) architecture for 3-D median filter were presented.
为了满足实时实现三维医学图像去斑应用的需要，本文提出一种新的实现三维中值滤波器的快速算法及其高性能VLSI结构。
The structured design of integrating software, hardware, computer architecture, VLSI technology and testability together, is introduced.
介绍了综合软件、硬件、计算机体系结构、超大规模集成技术和可测性的设计方法。
In this dissertation, we designed the architecture and the workflow of the analog VLSI layout automation tool.
本文设计了模拟集成电路版图设计自动化工具的流程。
In this dissertation, we designed the architecture and the workflow of the analog VLSI layout automation tool.
本文设计了模拟集成电路版图设计自动化工具的流程。
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