The latter provides the control and clock signals for the driving circuitry on screen and accomplishes the video data processing.

后者为屏上驱动电路提供控制、时钟信号，完成视频数据的处理。

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And for the request of video data processing, four inner buffers are designed, which are structured by dual body. They are realized by embedded array block in FPGA.

同时基于视频数据处理的需要，设计了四个具有双体存储结构的内部缓存器，由FPGA内部的嵌入式阵列块实现。

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And for the request of video data processing, four inner buffers are designed, which are structured by dual body. They are realized by embedded array block in FPGA.

同时基于视频数据处理的需要，设计了四个具有双体存储结构的内部缓存器，由FPGA内部的嵌入式阵列块实现。

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