All digital logic functions are used in the CPLD device VHDL language.
所有数字逻辑功能都在CPLD器件上用VHDL语言实现。
Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.
说明：利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。
This system is based on VHDL language, designed nine demonstrational experiments.
设计了以VHDL编程语言为基础，设计了九个单元演示实验。
The software design for MSP430 in C language is given and CPLD in VHDL language is developed.
完成了MSP430单片机C语言控制板的软件设计，并应用VHDL语言对硬件CPLD进行了开发。
The paper proposes a new method for Hanming encoder and Hanming decoder which is based on the VHDL language.
文章提出了一种新的基于VHDL语言的汉明码的编码和译码的实现方法。
The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。
VHDL language is the important tool of electronic design, and data object is one of essential language factors.
VHDL语言是现代电子设计的重要工具，数据对象是其中的重要语言要素。
The serial communication interface chip design was realized by application of schematic diagram and VHDL language.
采用自顶向下的设计方法，用原理图和VHDL语言这两种输入对串行通信接口芯片进行设计。
RISC microprocessor is developed by using modular design method and VHDL language based on FPGA and EDA technology.
基于FPGA和电子设计自动化技术。采用模块化设计的方法和VHDL语言，设计一个基于FPGA的RISC微处理器。
But the VHDL language simplifies the entire system significantly and improves the overall functions and reliability.
基于VHDL语言，将使整个系统大大简化，提高整体的性能和可靠性。
State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given.
CPLD的接口时序逻辑控制功能采用状态机工作方式实现，并给出了用VHDL编写的主要源代码。
My graduation project core duty is: Uses FPGA to manufacture one based on the VHDL language compilation digital voltmeter.
本人的结业设计的中心使命是：采用FPGA来制造一个基于VHDL言语编写的数字电压表。
The paper introduces the giving rise to and characteristic and the basic grammar structure of programming of VHDL language.
本文介绍了VHDL语言的产生、特点和程序设计的基本语法结构。
Summarized the concurrent statements and sequential statements of VHDL language, and described their types and the characteristic.
简单概述了VHDL语言的并行语句和顺序语句，描述了其种类和特点。
The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
CPU内核采用VHDL硬件描述语言输入，结合流行的EDA设计、综合、仿真工具，最后在FPGA上实现该内核。
This paper mainly talks about designing the protocol layer of USB2.0 with the programmable logical device as the carrier through the VHDL language.
本文在此主要通过VHDL语言，利用可编程逻辑器件作为载体来设计usb2.0的协议处理层模块。
The paper introduce the technique of EDA, on it, logical function has been stigmatized by VHDL language, the design of hardware become more flexible.
本文引入了电子设计自动化(EDA)技术，在EDA平台上使用硬件描述语言(VHDL)完成对硬件功能描述，使硬件设计更加灵活。
This design makes high use of hardware resource about FPGA, programming with VHDL language, achieving FIR filter with high sampling level based on FPGA.
该设计对FPGA硬件资源的利用高效合理，用VHDL编程，在FPGA中实现了高采样率的F IR滤波器。
Having analyzed the difference of the two languages, this paper provides a method of translating C language into VHDL language, and the method is implemented.
文章通过分析两种语言的区别，提出并实现了适于表达C语言描述内容的VHDL结构形式，并对几种C语言结构提出合理的转换方案。
And combinational logic circuits by using VHDL language and in two ways, comparing the merits of the two implementations and different design processes and ideas.
并且通过应用组合逻辑电路和VHDL语言实现两种方法，对照了两种实现方法的优劣及不同的设计流程和思想。
This paper presents advantage of M-sequences ciphers system by using m sequences as key sequences and proposes the design method of this system based on VHDL language.
文章介绍了用M序列为密钥序列的序列密码系统的优越性，提出了采用VHDL语言来设计这种序列密码系统的新方法。
VHDL language is used to describe, define the base pins, add read-write and compile schematics, create the JED files, and download JED files into CPLD to complete the design.
并用VHDL语言描述逻辑、定义管脚、增加读写、编译原理图、产生JED文件，将JED文件存入可编程逻辑器件以完成编程设计。
The VHDL language as an advanced hardware description language is playing a more and more important role in digital circuitry designs with its nimble and simple design style.
VHDL语言作为先进的硬件描述语言，也以其灵活、简洁的设计风格再电路设计中发挥着越来越重要的作用。
The system utilizes data-chosen-switches, microprocessor AT89C51 and complex logic device (CPLD). The software program is written by C language and VHDL language, respectively.
该系统数字部分主要利用拨码开关、单片机AT89C51，复杂可编程逻辑器件进行设计。
A full-function control system of counting is designed on a PLD device using VHDL language. It can measure and display the length and send out a control signal according to the set value.
利用VHDL语言在PLD器件上设计全功能计数控制装置，使其实现计量、显示长度并根据预置数输出控制信号的功能。
On the base of analyzing the structure and the design difficulty of the asymmetric synchronous FIFO, an asymmetric synchronous FIFO is achieved by using VHDL language and FPGA in this paper.
本文在分析了非对称同步fifo的结构特点及其设计难点的基础上，采用VHDL描述语言，并结合FPGA，实现了一种非对称同步fifo的设计。
This paper will describe how to realize the fiber communication be - tween points in the CNC net base on the CNC net character. This module is designed with VHDL language and realized with...
本论文将根据数控网络的这些特点，详细介绍如何在物理层，用VHDL语言设计一个满足这些要求的模块，通过光纤实现点对点的通信。
Through a simple and complete and typical 12-band counter VHDL design examples, to make preliminary understanding of VHDL expression and the resulting VHDL language phenomenon and statement rules.
通过一个简单完整而典型的12进制计数器的VHDL设计实例，来使大家初步了解用VHDL表达以及由此而引出的VHDL语言现象和语句规则。
Through a simple and complete and typical 12-band counter VHDL design examples, to make preliminary understanding of VHDL expression and the resulting VHDL language phenomenon and statement rules.
通过一个简单完整而典型的12进制计数器的VHDL设计实例，来使大家初步了解用VHDL表达以及由此而引出的VHDL语言现象和语句规则。
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