For more information on valid memory configurations, please see the system documentation on the technical support web site.
有关有效的内存配置的详细信息，请参阅技术支持Web站点上的系统说明文件。
As mentioned above, the edge of mapped memory — last valid address — is often known as the system break or the current break.
如前所述，被映射的内存的边界(最后一个有效地址)常被称为系统中断点或者当前中断点。
The RMO register is designed for each partition and is intended to facilitate each partition to reference address zero and yet a valid and unique address in the memory.
RMO 寄存器设计用于每个分区，并且可以帮助每个分区引用地址零、以及内存中有效的且唯一的地址。
This ensures that Heap dumps are taken after evidence of the memory leak is apparent, and with enough memory leakage to ensure the best chance of a valid analysis result.
这可以确保在确定内存泄漏之后获取堆转储，并通过足够的内存泄漏获得最有效的分析结果。
As you can see, this is a pseudo-leak. On the surface the amount of memory consumption looks really bad, but there is a completely valid reason.
你也能看到，这是一个伪溢出，从表面上看多占用的内存是很难看的，但是确实也是有必要的。
The described conversion is straight-forward and can be done in-place, i.e. the memory area holding the WKT string is modified directly to transform it to a valid SVG element string.
上述转换非常简单，可以一次完成，即，直接修改存放wkt字符串的存储区，将其转换为一个有效的SVG元素字符串。
But if the operating system has marked that Internet communications buffer region of memory as only being valid for containing data and NOT code, the hacker's attack will never get started.
但是，如果经营体制，标志着互联网通信缓冲区的记忆，因为只有被有效遏制数据，而不是代码，黑客的攻击将不会得开始。
"o" : A memory operand is allowed, but only if the address is offsettable. ie, adding a small offset to the address gives a valid address.
对内存的操作被允许，但是必须支持地址偏移值，即，对于给出的地址，加上一个偏移量，此时也是一个合法的地址。
According to the above discussion, we think, reciting from memory meaningful dialogue or short composition acquires language knowledge, is also a valid path which acquires speech.
根据以上的讨论，我们认为，背诵有意义的对话或短文是获得语言知识，也是获得语言能力的一条有效的途径。
Dynamic stack growth is the only situation in which access to an unmapped memory region, shown in white above, might be valid.
动态栈增长是唯一的情况中，接触到一个映射的内存区域，在白色上面所示，可能是有效的。
The results showed that: (1) the effect of the contents of visual working memory was significant. And the RTs were significantly longer in the invalid condition than in the valid condition.
结果发现：(1)不同视觉工作记忆内容条件下的反应时存在显著差异，无效信息条件下的反应时显著长于有效信息条件下的反应时。
And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.
对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。
And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.
对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。
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