According to a running operating system, an address translation controller accesses a corresponding address translation buffer to translate virtual addresses to real addresses.
根据正在运行的操作系统，地址转换控制器访问对应的地址转换缓冲器，以将虚拟地址转换成真实地址。
The performance improvements are due to the reduced translation look aside buffer (TLB) misses.
性能的提高归功于转换表缓存区(translationlook a side buffer,TLB)失败的减少。
To speed up address translation, there is a processor-on-a-chip (PoC) cache and associated logic called translation lookaside buffer (TLB).
为了加快地址转换，架构中有一个 processor-on-a-chip (PoC)缓存和相关的转换后备缓冲器 (TLB)逻辑。
The performance improvement is due to the reduction of Translation Lookaside Buffer (TLB) misses, which occurs because the TLB can now map to a much larger virtual memory range.
性能之所以得到了改进，是因为提高了TranslationLookasideBuffer (TLB)的命中率，这是因为TLB可以映射到更大的虚拟内存范围。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
为了提高CPU的速度和更有效的管理物理内存，一般都采用转换查找缓冲器（TLB）将虚拟地址转换为物理地址。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
为了提高CPU的速度和更有效的管理物理内存，一般都采用转换查找缓冲器（TLB）将虚拟地址转换为物理地址。
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