In this paper, a SVPWM signal generator is designed with VHDL. This signal generator can transform time signal into SVPWM trigger signal successfully with good anti-jamming capability.
本文利用VHDL硬件描述语言设计了一种SVPWM信号发生器，该信号发生器不仅成功实现了输入时间信号到SVPWM触发信号的转换，而且具有良好的抗干扰能力。
In this paper, a SVPWM signal generator is designed with VHDL. This signal generator can transform time signal into SVPWM trigger signal successfully with good anti-jamming capability.
本文利用VHDL硬件描述语言设计了一种SVPWM信号发生器，该信号发生器不仅成功实现了输入时间信号到SVPWM触发信号的转换，而且具有良好的抗干扰能力。
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