Through a large number of computer digital simulation experiments, this paper discusses the shift time of free flight and little single impulse individually.
本文通过大量的计算机数字仿真实验，研究了无冲量自由飞行轨迹与单个小冲量飞行轨迹的转移时间。
Traditional simulated signal can be replaced by digital signal. Human beings is from simulation time to digital Age.
传统的模拟信号都可以用数字信号来代替，人类正在从模拟时代向数字时代迈进。
All-digital terrain following (TF ) simulation system and hardware-in-loop real-time terrain follow simulation system are designed to verify the TF algorithms.
本文开发了全数字地形跟随仿真系统与半物理地形跟随仿真系统两个系统以验证所设计的地形跟随算法。
By digital simulation and detection of gearbox fault signal the detection effect of the novel bilinear time-frequency transform is validated for the transient components in complex signal.
通过数字模拟实验与齿轮箱故障信号检测，验证了新的双线性时间-频率分布对复杂信号中瞬时分量的探测效果。
The system simulation and practical physical simulation test show, that the time response of the digital control system is better than that of hydro pneumatic control system.
系统仿真和半物理模拟试验表明，数字控制系统的时间响应，在相同干扰情况下，优于气动液压式控制系统。
The dynamic and digital real-time simulation of power system is believed as an indispensable tool for power system planning, protective and control devices designing and testing.
电力系统动态数字实时仿真已成为规划电力系统，设计与检验电力系统控制、保护以及调度设备的主要工具。
To ensure the real-time simulation, the step length of the parallel digital computer must be related not only to the complexity of the object but also to the number of the bigital computers selected.
为了保证进行实时仿真，并行数字计算机的计算步长除与对象复杂程度有关外，还与所选数字计算机数目有关，选取较小步长必须使用较多计算机。
CAE platform can support the whole cycle of the design of FACTS equipment, including theoretical design, digital simulation, regulation on line, physical experiment, and real time operation.
CAE平台作为一个一体化的环境，能支持FACTS装置控制器设计的整个生命周期，即理论设计、数字仿真、在线调试、动模实验和实时运行。
Finally, the performances of this digital demodulator are tested through the simulation of BER and the system joint lock-time, and a carrier recovery module is implemented in FPGA.
最后，通过对误码性能和系统联合锁定时间进行仿真，验证了数字解调器性能，并在FPGA中实现了载波恢复模块。
Finally, the performances of this digital demodulator are tested through the simulation of BER and the system joint lock-time, and a carrier recovery module is implemented in FPGA.
最后，通过对误码性能和系统联合锁定时间进行仿真，验证了数字解调器性能，并在FPGA中实现了载波恢复模块。
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