If you looked only at the clock speeds of microprocessor chips, you might well think so.
如果你仅仅参照微处理器芯片的时钟速度，你可能会这么想。
For years, Intel has consistently improved the performance of its chips by making them run at higher and higher clock speeds (measured in MHz or GHz). But it has now hit a wall.
多年以来，英特尔通过提高越来越快的时钟频率(以MHz或者GHz计)，持续不断地改进了芯片的性能，但现在撞上了南墙。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module.
系统主芯片采用EP1K100 QC 208 - 3，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well.
除了可以通过提高芯片工作频率来提高译码吞吐率，还需要研究并行译码结构及其实现方案。
Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well.
除了可以通过提高芯片工作频率来提高译码吞吐率，还需要研究并行译码结构及其实现方案。
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