• The company already has collected test pattern images that demonstrate telescope image quality and focal plane functionality.

    公司已经收集了试验模式图像用于望远镜成像质量和焦平面功能。

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  • As I proceed with the examples, I'll highlight whether a given test pattern verifies the crosscutting functionality, the specification, or both.

    在完成这个例子的过程中,我将强调给定的测试模式是验证横切功能、规范,还是两者同时验证。

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  • How to generate CPU test pattern efficiently is a big problem to people who write test programs.

    如何科学有效地生成CPU测试图形,是困扰测试程序开发人员的一个难题。

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  • For example, you can code a load test plug-in to set or modify the load test pattern while the load test is running.

    例如,可以编写负载测试插件代码,以便在负载测试运行过程中设置或修改负载测试模式。

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  • This paper studies the crosstalk fault and its methods of test pattern generation in high-speed interconnect circuits.

    本论文针对高速互连电路串扰型故障及测试生成方法进行研究。

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  • The paper proposes controlling input values tracing algorithm and test derivation algorithm based on test pattern generation using satisfiability.

    以组合电路的满足性测试生成算法为基础,提出了控制输入跟踪算法和测试衍生算法。

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  • Based on the double bridge structure of microelectronics test pattern, the method of defect model parameter extraction is presented in this paper.

    基于微电子测试双桥结构,本文给出了缺陷特征参数提取方法。

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  • A first memory (102) is configured to store pixel values for transitions between portions of the video test pattern and configured to store a repeated pixel value.

    第一存储器(102)被配置用于存储用于视频测试图案的各部分之间的过渡的像素值,并被配置用于存储重复的像素值。

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  • Therefore, how to quickly generate accurate functional test pattern has turned to be the important factor in lower production test cost and shorter time to market.

    因此,如何快速产生准确的功能测试向量就成为降低产品测试成本和缩短产品上市时间的关键因素。

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  • In discussing the response-based testing technologies, the C/S test pattern is put forward in the interact test of Object-Oriented class according to the C/S system idea.

    在讨论基于响应的测试技术时,根据C/S系统的思想,本文提出了面向对象类之间交互测试的C/S测试模式。

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  • The invention relates to the test field of integrated circuits and discloses a low power consumption test pattern generator of an integrated circuit and a test method thereof.

    本发明涉及集成电路测试领域,公开了一种集成电路的低功耗测试图形生成器及其测试方法。

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  • For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.

    对于所有的实验电路,通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器,本策略可以编码所有的确定性测试向量。

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  • In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.

    为了减少测试向量的存储需求,提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。

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  • In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.

    为了减少测试向量的存储需求,提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。

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