A new test data compression technique based on encoding series and alternation sequences is proposed.
提出一种新的基于连续和交替序列编码的测试数据压缩方案。
The paper proposed a new Selected Variable-length Input Coding (SVIC) for System on Chip (SOC) test data compression.
本文针对SOC测试数据压缩，提出了一种新的可挑选变长输入编码(SVIC)方案。
Aiming at a large number of sequential data blocks existing in test set, a new test data compression scheme based on power division is presented.
针对测试集中存在大量的连续数据块，本文提出了一种基于幂次数划分的测试数据压缩方法。
A test data compression scheme based on fixed and variable length coding (FAVLC) is presented, by using which the test data can be compressed efficiently.
文章提出了一种混合定变长码的测试数据压缩方案，该方案可以有效压缩芯片测试数据量。
In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.
为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。
In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.
为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。
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