The proposed method USES the compatibility between test vectors to reduce test application time.
该方法利用了测试向量之间的相容性，降低测试应用时间。
Recently, reducing test application time and test data volume is a direction of effort in SoC design .
目前，减少测试应用时间和测试数据容量是测试领域的努力方向。
There are three serious problems: These are test application time, test data volume, and test power consumption.
其中比较严重的问题有三个：它们分别是测试时间、测试数据量和测试功耗。
To overcome the shortage, this thesis proposes a method for test application time reduction based on TSP problem.
为了克服这一缺陷，本文提出了一种基于TSP问题降低测试应用时间的方法。
The proposed method can reduce test application time and test storage using a simple structure that just added a small amount of hardware.
该方法结构简单，只需要添加少量的硬件，却能很好地降低测试应用时间和测试数据存储量。
The experimental results show that, the method can effectively reduce test application time without additional hardware costs.
实验结果表明该方法有效地减少测试应用时间，并且不需要额外的硬件代价。
Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized.
测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给测试存取机制的方法，以使得总的测试时间最少。
A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.
一种基于扫描链阻塞技术的扫描测试结构被提出来，该结构有效地降低了测试功耗，但其测试应用时间较长。
A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.
一种基于扫描链阻塞技术的扫描测试结构被提出来，该结构有效地降低了测试功耗，但其测试应用时间较长。
应用推荐