Includes a rich set of functions to test access control requirements, such as the user's IP address, time and date, or whether the user's name appears in a given list.
包括用于测试访问控制要求的丰富功能集，例如用户的IP地址、时间和日期，或用户的名称是否出现在给定的列表中。
Joint test Action Group designed a common chip boundary-scan structure and test access port criterion which is called JTAG standard to support testing on-board chip or logic.
为支持板上芯片或逻辑的测试，联合测试行动小组专门设计和定义了一种通用的芯片边界扫描结构及其测试访问端口规范，称为JTAG标准。
Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized.
测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给测试存取机制的方法，以使得总的测试时间最少。
This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented fort…
本文论述了板级边界扫描测试存取口的故障模型和测试原理，并针对全边界扫描印制板提出了一种故障覆盖率高、测试时间短的测试算法。
The test access port and test logic architecture and protocol of 1149.4 and 1149.1 standards are analyzed, and behavior models for ABM and DBM are put forward.
文章分析了1149.4和1149.1标准的测试访问端口，以及测试逻辑结构和测试协议的异同，提出了模拟边界 扫描单元ABM和数字边界 扫描单元DBM的行为模型；
The easy JTAG is introduced to control Test Access port (TAP) by computer parallel port.
采用简易JTAG接口，通过计算机并口控制测试访问端口。
As is a new hardware device for network monitoring, TAP (Test Access Port) provides a method for obtaining the network traffic without disrupting the normal traffic.
是一种新兴的用于网络监测的硬件设备，它提供了一种在不中断网络正常流量的情况下，获得网络流量的方法。
As is a new hardware device for network monitoring, TAP (Test Access Port) provides a method for obtaining the network traffic without disrupting the normal traffic.
是一种新兴的用于网络监测的硬件设备，它提供了一种在不中断网络正常流量的情况下，获得网络流量的方法。
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