Various MOSFET tests require making low current measurements. Some of these tests include gate leakage, leakage current vs. temperature, substrate to-drain leakage, and sub-threshold current.
各种MOSFET测试都要求进行弱电流的测量。这些测试包括栅极漏电、泄漏电流与温度的关系、衬底对漏极的漏电和亚阈区电流等。
Based on simulation, the characteristics and mechanisms of failure on a deep sub-micron grounded-gate NMOS (GGNMOS) are studied under TLP (transmission line pulse) stress.
对TLP(传输线脉冲)应力下深亚微米ggnmos器件的特性和失效机理进行了仿真研究。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
To convert a gate circuit to a Boolean expression, label each gate output with a Boolean sub-expression corresponding to the gates' input signals, until a final expression is reached at the last gate.
要转换选通电路成一个布尔表示式，标记每个门的产品以对应于门的输入的一个布尔次级表示信号，直到最后一个表示信号到达最后门。
Second, the method determines the optimum valve gate location in each sub-moulding by applying equal-flow-path-length algorithm.
然后按照等流长算法求各分区的最佳阀浇口位置；
Second, the method determines the optimum valve gate location in each sub-moulding by applying equal-flow-path-length algorithm.
然后按照等流长算法求各分区的最佳阀浇口位置；
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