Operation of the clock timing used in the simulation of the way rather than the interruption of conventional methods.
操作时钟时采用了模拟时序的方式而不是常规的中断方式。
Simulation results showed that, with 5 CNC mode tuning capacitor arrays, the tuning time error was no more than three clock cycles, which meets requirements of the system.
仿真结果表明，采用5位数控方式调谐电容阵列，调谐时间误差不超过三个时钟周期，满足系统要求。
With time series simulation software, the CPU's I/O ports simulate I2C bus and exchange data with clock chips, temperature humidity sensors, memory chips and other devices.
采用软件模拟时序使CPU的I/O口模拟I2C总线，实现了单片机与时钟芯片、温湿度传感器、存储芯片等器件的数据交换。
A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.
结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
It is demonstrated by simulation results that MBBS reduces the messages needed for global synchronization and reaches higher clock synchronization accuracy in multilayer topology.
实验结果表明，在多层网络拓扑下，MBBS减少了全局时钟同步所需的信息数目，提高了网络时钟同步的精度。
It is demonstrated by simulation results that MBBS reduces the messages needed for global synchronization and reaches higher clock synchronization accuracy in multilayer topology.
实验结果表明，在多层网络拓扑下，MBBS减少了全局时钟同步所需的信息数目，提高了网络时钟同步的精度。
应用推荐