Compared with the traditional serial multiplier, it can obtain twice speed-up.
与传统的移位乘法器相比，它将乘法器速度提高一倍。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The discussions include the design of multiplier, ALU and serial port; almost cover all the important aspect of the data path design.
分别对乘法器、ALU和串口的设计进行了讨论，几乎覆盖了数据通路设计的各个方面。
The discussions include the design of multiplier, ALU and serial port; almost cover all the important aspect of the data path design.
分别对乘法器、ALU和串口的设计进行了讨论，几乎覆盖了数据通路设计的各个方面。
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