A full wave analysis of lossy interconnection lines on doped semiconductor substrates in high speed integrated circuits is carried out by means of a finite difference time domain (FDTD) approach.
本文首次利用时域有限差分(FDTD)法分析了高速集成电路芯片内半导体基片上的有耗互连传输线的电特性。
The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines.
该半导体存储器件包含连接到一对位线的位线感测放大器。
It is composed by fiber delay lines, an optical waveguide switching array and a nonlinear semiconductor optical amplifier.
这种缓存器是由光纤延迟线、光波导开关阵及非线性半导体光放大器构成。
This optical buffer is composed with optical fiber delay lines, optical waveguide switching array and nonlinear semiconductor amplifier.
这种缓存器由光纤延迟线、光波导开关阵及非线性半导体光放大器构成。
Based on the classification on the scheduling for semiconductor wafer lines, the modular and reconfigurable framework is proposed.
在分析半导体生产线调度分类的基础上，提出了组件化可重构半导体生产线调度体系结构。
Based on the classification on the scheduling for semiconductor wafer lines, the modular and reconfigurable framework is proposed.
在分析半导体生产线调度分类的基础上，提出了组件化可重构半导体生产线调度体系结构。
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