An improved current-controlled tristate switching power amplifier based on sample-hold strategy is proposed in this paper.
提出一种改进的基于采样-保持策略的电流三态调制开关功放。
The Celts used these bowls of unleavened bread to hold a variety of fillings, including - as I discover when Wood hands me a sample - a tasty mixture of smoked fish, leek, hazelnuts and cream.
凯尔特人用这种未发酵的面包“碗”来放各种各样的食物，我发现伍德今天放的食物就有很多，包括一种烟熏鱼、韭葱、榛子和奶油的混合物。
To show off your work, you will need to create two projects: one to hold your Groovy wrapper code and one to hold your sample Ajax UI.
为了展示您的工作，您需要创建两个项目：一个存放groovy包装器代码，另一个用于存放示例AjaxUI。
This is the strength of Skyworks company, and we do hold our titles like sample ping-pong or now table tennis.
这就是Skyworks公司的优势，我们也很重视我们的品牌，比如我们的乒乓，又叫桌球游戏。
Its advanced current sensing circuitry employs sample and hold methods to provide a precise average current signal.
其先进的电流检测电路采用采样和保持方法，以提供精确的平均电流信号。
The output of the sample-and-hold system now goes into an analog-to-digital converter .
取样和保持系统的输出现在又进入一个模数转换器。
The part features very tight aperture delay matching between the two input sample and hold amplifiers.
该器件的两个输入采样保持放大器之间具备高匹配度的孔径延迟。
On the basis of analyzing the common methods of background magnetic field compensation, a new automatic compensation method based on sample and hold circuit is put forward.
在分析磁通门常用背景磁场补偿方法基础上，提出一种新的采样保持电路自动补偿方法。
The output of the sample - and - hold system now goes into an analog - to - digital converter .
取样和保持系统的输出现在又进入一个模数转换器。
The analog input circuitry contains the analog multiplexer, the instrumentation amplifier, and the sample-and-hold circuitry.
模拟输入电路包含模拟多路复用器，仪表放大器，以及采样保持电路。
Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。
Two alligator clips on the end will hold a variety of bag sizes, making sample collection easy and fast.
柄端两个鳄鱼夹可以配合使用多种尺寸的无菌取样袋子，使样品收集更容易，更快速。
Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。
Sample the negative voltage on the diode series with IGBT by Peak hold switch circuit, and cut-in A/D module in the DSP, compared with setting value.
通过电压峰值采样保持电路对IGBT串联二极管反压值进行采样，后经DSP A/D转换模块与反压设定值进行比较。
Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
设计了一个用于流水线型模数转换器的低压采样保持电路。
The intensity of a pulse emitting laser can be controlled constantly and continuously while recording data without using test emissions or a high speed sample hold circuit.
对在记录数据时处于脉冲发光状态的激光，不用试验发光或高速抽样保持电路，就能经常连续地控制其强度。
The receiver circuits in the chip adopts novel optimized topology in order to increase the precision of sample, hold and process;
在接收器电路的设计中，论文采用了经优化的新型拓扑结构，提高了数据采样和接收精度；
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference.
这是一款完整的单芯片adc，内置片内高性能、低噪声采样保持放大器和可编程基准电压源。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
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