The deputy mayor of the Paris suburb of Levallois-Perret and a close friend of Sarkozy's told RTL radio this thing.
巴黎郊区勒瓦卢瓦-佩雷的副市长和萨科齐的亲密朋友告诉了RTL电台这件事。
That proves that he is doing well he told RTL radio.
这证实他做得很好，他告诉RTL电台。
The IC design method base on RTL has been widely used.
集成电路设计在寄存器传输级的设计方法已经非常成熟。
RTL hybrid satisfiability solving is the key technique of RTL verification.
RTL混合可满足性求解是RTL验证中的关键技术。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Warrants for RTL are analyzed in view of safety and traffic operation efficiency.
从安全和交通效率两个方面研究左转相位的设置。
The problem with RTL is that the optimizations it enables are those close to the target.
RTL的问题是，它支持的优化是接近于目标的。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
Finally, the SSA trees are converted into RTL, which the back end USES for target code generation.
最后，ssa树被转换成rtl，后者被后端用于目标生成代码。
To do this, the optimizer USES the RTL to create fast or more compact code (or both, when possible).
为此，优化器使用RTL创建快速的或紧凑的代码(或者两者兼顾)。
Simulation results on the function of RTL codes, as well as analysis on the performances, are presented.
给出了RTL代码的功能仿真结果和性能分析，并且已经成功应用于实际系统。
This paper proposes and implements a novel verification and RTL-Level bug locating method for microprocessors.
本文提出并实现了一种新的基于指令分解的微处理器验证与RTL级错误定位方法。
This is the lie from Germany RTL TV channel. It used the picture from Nepal again. But it says that's from China.
这是来自德国RTLTV频道的谎言。又使用了尼泊尔的图片。但是声称来自中国。
In theory, a logic synthesis tool guarantees that the first netlist is logically equivalent to the RTL source code.
在理论上，逻辑综合工具，保证第一网表是合乎逻辑相当于RTL源代码。
Anna-Bell told the German television station RTL: "we wanted to get married and so we just thought: 'Let's go there."'
Anna - Bell告诉德国电视台RTL说：“我们想结婚，于是就想，那就去吧！”
RTL and FPGA are used to validate high-level models while software tools are used for tasks such as workload analysis.
RTL和FPGA主要用于验证高级语言模型，各种辅助工具可以用于工作负载的分析和优化。
The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
By comparing the trace of simulator with that of the processor RTL model, design faults can be quickly and accurately located.
模拟器的运行结果与处理器RTL模型的结果进行对比，大大方便了对RTL模型的验证和查错。
RTL(register transfer level) functional verification system for package assembly function in IPOA application is illustrated in this paper.
介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。
Still others would say that ESL refers to anything that's at a higher level of abstraction than register transfer level (RTL) representations.
还有一些人会说esl是优于寄存器传输级(rtl)的更高的抽象层次。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
Transaction level modeling hides unnecessary details. The communication at transaction level is method calls in comparison with signals and pins at RTL.
事务级建模在RTL级之上，忽略了不必要的细节，把模块之间的通信方式从管脚和信号方式抽象为函数调用。
An alternative way to solve this is to formally prove that the RTL code and the netlist synthesized from it have exactly the same behavior in all cases.
另一种方式来解决，这是正式证明，RTL代码和网表合成具有完全相同的行为在所有的案件。
The three key modules are all presented as RTL level design and module functional simulation. The deinterlacing system's FPGA design is in the last chapter.
本文对于这三个去隔行系统的关键模块都给出了RTL级设计和模块的功能仿真，并在最后一章中给出了去隔行系统的FPGA设计。
This paper constructs the function simulation platform for buffer manager and the whole system, and validates the design on the platform after the RTL design.
在完成该单元的RTL级设计的基础上，进一步构建了该单元及整个系统的功能仿真平台，在该平台上验证了设计的正确性。
Before the appearance of RTL strategy, Postpone logistics strategy, JIT strategy and other logistics strategies have been put widely into the practice of logistics.
在实时物流战略产生之前，已经有延迟物流战略、准时制生产战略等其他物流战略被广泛地运用在企业的物流实践中。
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
The work of this dissertation is to complete the RTL design and verification of CLB-PVCI bus bridge after studying and analyzing the CLB bus protocol and PVCI protocol.
本论文工作就是在研究和分析CLB总线协议和PVCI协议的基础上，完成CLB - PVCI总线桥的RTL设计和验证。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
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