The implementation carries out the standard-cell design of RS decoder, improves the velocity of decoding efficiently and simplifies the hard - ware design.
该方法实现译码器的标准单元化设计，并且有效提高译码的速度，简化硬件设计。
In more research, a new multiplex pipeline is presented and is used to design multi-channel RS decoder. The proposed scheme greatly reduce resources per channel.
在达到设计要求的基础上本文对RS译码器做了进一步的研究，利用一种新型的复用流水线结构实现了多路RS译码器，有效的减少了每路译码所占用的资源。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
The paper items from a project on developing communication devices. The implementation of CRC-RS decoder in the project asks for an adoption of RS and extended shortened CRC codes.
本论文内容来源于某通信设备研制项目，该项目中的“CRC-RS译码器的设计”要求采用RS和扩展缩短CRC码来实现。
The fourth chapter is this paper's emphasis , focuses on the byte processing part(outer code) module by module: data reverse transformer, de-randomizer, RS decoder, de-interleaver and synchronization.
第四章是本文的主要部分，开始分模块说明对字节处理部分的研究：数据格式反变换、解扰、RS译码、去交织和同步头搜索。
RS hardware decoder can be used in the ground receiver system.
R S码硬件译码器也可应用于地面接收系统中。
Then, the code theory and time-domain iterative decode algorithm of RS code is introduced, RS coder and decoder are designed and implemented in this base.
接着介绍了R S码的编码原理和时域迭代译码算法，在此基础上设计实现RS码编码器和译码器。
In this paper, rs (204,188) encoder and decoder is designed, which can correct 8 errors to the maximum.
本论文设计的是RS(204,188)码的编码器和译码器，最多能纠正8个错误。
In this paper, rs (204,188) encoder and decoder is designed, which can correct 8 errors to the maximum.
本论文设计的是RS(204,188)码的编码器和译码器，最多能纠正8个错误。
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