Output signal distort of the drive circuit due to rc delay in peripheral integrated AMLCD is discussed.
讨论了AMLCD周边集成驱动电路中的延迟导致的输出信号的失真。
Low resistivity of gate line is very useful for large size panel by overcoming rc delay, also, for small size application with fine pitch process.
为克服大尺寸显示面板中反应时间的延迟问题，采用低阻栅线是十分有益的，同样在小尺寸面板上也存在这种相互匹配的过程。
Its showed that the auto optimization function of ANSYS can help to rapidly and intuitively seek the optimally geometrical parameters which minimize the RC delay.
应用表明：ANSYS的模拟精度高，图形显示功能强。应用ANSYS自动寻优功能使RC延迟最佳化几何参数的寻找较为迅速和直观。
An approach for analyzing coupling rc interconnect delay based on "effective capacitance" is presented.
基于“有效电容”的概念提出了一种分析两相邻耦合r C互连延时的方法。
An approach for analyzing coupling rc interconnect delay based on "effective capacitance" is presented.
基于“有效电容”的概念提出了一种分析两相邻耦合r C互连延时的方法。
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