A digital hardware control scheme of shunt active power filter (SAPF) based on field programmable gate arrays (FPGA) is introduced.
提出一种基于现场可编程门阵列(FPGA)的并联型有源电力滤波器(SAPF)的控制器方案。
On this basis, a prototype is developed with a high speed digital signal processor (DSP), huge field-programmable gate arrays (FPGAs) and real-time software.
在此基础上，采用高速数字信号处理器（DSP）、大规模现场可编程门阵列（FPGA）和实时软件进行系统设计，完成了原理样机的研制。
This paper presents a fine-grained pipeline algorithm for lu decomposition with column partial pivoting and gives the description of its implementation on field-programmable gate arrays (FPGA).
提出了一种可以进行列主元选取的细粒度lu分解流水线算法并在现场编程门阵列(FPGA)上得到了实现。
In this dissertation, Field Programmable Gate Arrays (FPGA) chip is studied to develop and design the fine interpolation chip.
本文着重研究用现场可编程门阵列(FPGA)来开发设计精插补芯片。
In this dissertation, Field Programmable Gate Arrays (FPGA) chip is studied to develop and design the fine interpolation chip.
本文着重研究用现场可编程门阵列(FPGA)来开发设计精插补芯片。
应用推荐