The application of complex programmable logic device (CPLD) and digital programmable delay line AD9501 in the system is described.
介绍了复杂可编程器件(CPLD)和可编程数字延迟线(AD95 0 1)在系统中的应用。
In this article, a programmable pulse delay unit based on EPLD is discussed.
文中讨论了基于EPLD的可编程脉冲延时单元。
In the case of FPGAs, the number of blocks used will also greatly influence the final delay after routing because most of the delays is the wiring delays due to the programmable interconnect existed.
在FPGA的情况下，所使用的元胞块数量也会在很大程度上影响布线后的最终延迟，因为大多数延迟是由存在的可编程互连所引起的布线延迟。
The two-wire serial interface enables outputs to be margined, tuned and ramped up and down at programmable slew rates with sequenced delay times.
两线串行接口，实现输出会被强制平仓，调整和上升和下降，在可编程的摆率与测序的延迟时间。 输入和输出电压，以及输入和输出电流和温度是可读的。
This is the first report about general developing aspect of SAW programmable tapped delay line (SAW-PTDL)in our institute.
报道声表面波可程序抽头延迟线的研制情况。
Additional features include: programmable transition delay, low quiescent current, higher efficiency at light loads, and high speed control to quickly turn off both gate drivers.
其它附加功能包括：可编程跳变延时、低静态电流、在轻载时提供更高的效率，以及快速关断两个驱动器的高速控制。
A new digital beam forming (DBF) method is proposed. It combines the parallel delay LMS (PDLMS) algorithm and the field programmable gate array (FPGA).
采用高并行度的并行延时最小均方(PDLMS)算法，用现场可编程门阵列(FPGA)实现自适应数字波束形成模块。
The programmable pulse delay is implemented by EPLD.
可编程脉冲延时是由EPLD来实现的。
A 16 channels programmable time delay VME module is introduced in this paper.
本文介绍了一个16通道的程控时间延迟vme插件。
This paper reports a 31 bit low frequency SAW programmable tapped delay line. It is a key device in signal processing of interference free spread spectrum communication system.
文章报道的31位声表面波低频可程序抽头延迟线是一种用于扩频抗干扰通信系统所用的关键信号处理器件。
A new delay partition method is also adopted to improve the speed of the post-scale counter, which is used to realize the programmable phase shift and duty cycle.
本文还提出了一种延时分割方法以提高用于实现相移和占空比调节功能的后端分频器的速度。
A new delay partition method is also adopted to improve the speed of the post-scale counter, which is used to realize the programmable phase shift and duty cycle.
本文还提出了一种延时分割方法以提高用于实现相移和占空比调节功能的后端分频器的速度。
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