PLL circuit is adopted in order to control video signal synchronization.
系统中采用锁相环路控制视频同步。
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
The intermediate frequency circuit includes QPSK modulation based on HFA3724, PLL circuit based on MB1502.
中频部分主要由HFA3724正交调制解调器和基于MB1502的锁相频率合成电路等组成。
The PLL circuit has been designed in the controller to meet the requirement of high-speed and accurate sampling.
为满足高速和精确的采样，论文在控制器硬件中设计了锁相环电路。
This paper discusses the influence of mixer on the phase lock-loop (PLL) circuit of a local oscillator. In mixer, local signal is produced by the PLL circuit.
本文讨论了采用锁相环路作为本振信号的混频器对本振锁相环路的影响。
Introduces the basic principle of phase-locked loop and NE564 PLL circuit structure and properties, and the use of phase-locked NE564 demodulating circuit and phase-locked frequency circuit.
介绍了锁相环的基本原理和锁相环ne564的电路结构和性能，及其用ne564构成的锁相解调电路和锁相倍频电路。
Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.
分析了锁相环的基本原理和实现，并对射频电路设计理论和阻抗匹配问题进行了探究。
The PLL full synchronization video detector circuit is educed by feature and troubles of quasi-synchronization video detector.
由准同步视频检波的特点及其存在的问题引出锁相环（ PLL）完全同步视频检波电路。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.
模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip.
本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。
The PLL correction circuit enables input signal to multiply with changed frequency doubling factor during correction intervals.
PLL电路在校正间隔期间使输入信号乘以改变后的倍 频因子。
Now the full integrated PLL (phase locked loop) chip is used widely in radio frequency circuit.
全集成锁相环芯片目前在射频电路中应用很广泛。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
The paper introduces the principle of PLL clock synthesizer and the structure of MC12429, designs the circuit of the High Frequency clock synthesizer.
本文介绍了PLL合成时钟源的原理，介绍了MC 12429的结构，设计出了高频时钟源电路图。
The paper introduces the principle of PLL clock synthesizer and the structure of MC12429, designs the circuit of the High Frequency clock synthesizer.
本文介绍了PLL合成时钟源的原理，介绍了MC 12429的结构，设计出了高频时钟源电路图。
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