The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.
模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
PLL is used for generating carry synchronization signal.
采用平方环实现载波同步信号的提取。
Outputs serial data transferred from the PLL to the controller.
从PLL输出串行信号到控制器。
PLL circuit is adopted in order to control video signal synchronization.
系统中采用锁相环路控制视频同步。
DDS-driven PLL frequency synthesizer architecture is given in this paper.
给出了一种基于DDS驱动PLL的频率综合器结构。
The PLL has different un-locked threshold value in different jamming model.
环路在不同干扰样式下的失锁门限不尽相同。
High stability PLL-modulator and high sensitivity receiving demodulator are introduced.
介绍了高稳定锁相调制和高灵敏度的接收解调。
It also give an improved method for PLL (phase locked loop) to extract coherent carrier.
本文还对相干载波提取中的锁相环提出了一种改进方法。
The authors propose an improved phased locked loop (PLL) architecture with dual control paths.
提出一种改进的双控制通路锁相环结构。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
In this article, PLL theory, design of loop filter and phase noise theory are introduced at first.
本文先介绍了锁相环的工作原理，环路滤波器的设计并对相位噪声的理论进行了阐述。
A new phase noise estimate method for millimeter wave double PLL frequency synthesizer is presented.
提出了一种新的毫米波双环锁相源相位噪声估测方法。
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
The working state of all points in the PLL can be visibly displayed, with high ability in aid analyses.
锁相环路各点工作状态均可用图形直观显示，辅助分析能力强。
A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper.
提出了一种全新的电荷泵锁相环的行为级建模方法。
The intermediate frequency circuit includes QPSK modulation based on HFA3724, PLL circuit based on MB1502.
中频部分主要由HFA3724正交调制解调器和基于MB1502的锁相频率合成电路等组成。
But if the Doppler frequency offset exceed the capture range of PLL, the carrier synchronization will fail.
但是，一旦多普勒频移超出了锁相环的频率捕捉范围，就无法完成载频同步。
The nonlinear characteristics of PLL system are analyzed comprehensively in this thesis for the first time.
首次对电机锁相控制系统的非线性问题进行了较全面的研究工作。
USPIO-PLL, as an intracellular contrast agent, can label endothelial progenitor cells with high efficiency.
利用USPIO - PLL作为细胞内造影剂可以高效标记内皮祖细胞。
In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.
在锁相环频率合成器中，双模前置分频器是一个速度瓶颈。
A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.
提出了一种面向系统数学模型的模块连接式锁相环路计算机辅助分析方法。
The technology of PLL has always been the research emphasis in the field of measurement and control of power system.
锁相同步技术一直都是电力系统测控领域的研究重点。
Then some analyses are followed on the operation principle of each blocks and their influence on the PLL output signals.
然后分析了锁相环中各个模块的工作原理以及它们对锁相环输出的影响。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.
本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition, low jitter, and wide tuning range.
提出了一种快捕获，低抖动，宽调节范围的增益自适应锁相环的设计。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
Considering the characteristics of PLL, the dual self-excited driving circuits for capacitance micro-machined gyroscope are designed.
结合锁相环的特性，设计一种电容式微机械陀螺双环路自激驱动电路。
It analyzes the transient effect of frequency step of DDS on the PLL output response, and puts forward a corresponding improving way.
分析了DDS频率阶跃对于PLL输出响应的瞬态影响，并且给出了相应的改善方法。
Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.
前者在常规的采用电压外环、电流内环的双闭环控制基础上，搭建数字锁相环、数字滤波器。
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