The gappy clock is recovered by the PLL.
利用锁相环完成了码速恢复。
PLL is used for generating carry synchronization signal.
采用平方环实现载波同步信号的提取。
Outputs serial data transferred from the PLL to the controller.
从PLL输出串行信号到控制器。
PLL circuit is adopted in order to control video signal synchronization.
系统中采用锁相环路控制视频同步。
DDS-driven PLL frequency synthesizer architecture is given in this paper.
给出了一种基于DDS驱动PLL的频率综合器结构。
The PLL has different un-locked threshold value in different jamming model.
环路在不同干扰样式下的失锁门限不尽相同。
High stability PLL-modulator and high sensitivity receiving demodulator are introduced.
介绍了高稳定锁相调制和高灵敏度的接收解调。
In the field of communications, PLL synthesizers playing an increasingly important role.
在通信领域中，锁相环频率合成器起着越来越重要的角色。
It also give an improved method for PLL (phase locked loop) to extract coherent carrier.
本文还对相干载波提取中的锁相环提出了一种改进方法。
The authors propose an improved phased locked loop (PLL) architecture with dual control paths.
提出一种改进的双控制通路锁相环结构。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。
A new phase noise estimate method for millimeter wave double PLL frequency synthesizer is presented.
提出了一种新的毫米波双环锁相源相位噪声估测方法。
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
The working state of all points in the PLL can be visibly displayed, with high ability in aid analyses.
锁相环路各点工作状态均可用图形直观显示，辅助分析能力强。
Simulation results show the PLL clock frequency multiplier has lower phase noise and shorter capture time.
结果表明，PLL倍频器具有较低的噪声和较高的捕获速度。
The nonlinear characteristics of PLL system are analyzed comprehensively in this thesis for the first time.
首次对电机锁相控制系统的非线性问题进行了较全面的研究工作。
In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.
在锁相环频率合成器中，双模前置分频器是一个速度瓶颈。
A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.
提出了一种面向系统数学模型的模块连接式锁相环路计算机辅助分析方法。
DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.
PLL混合频率合成技术能综合两者的优点，已成为现今频率合成领域的重要研究方向。
In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.
本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。
The PLL full synchronization video detector circuit is educed by feature and troubles of quasi-synchronization video detector.
由准同步视频检波的特点及其存在的问题引出锁相环（ PLL）完全同步视频检波电路。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.
当水平的同步和振动者频率之间的巧合被发现的时候，搜寻模态被正常PLL操作代替。
Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL.
在我们准备为锁相环找到最优配置之前，首先要考虑如何找到锁相环的所有配置。
The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.
本文正是为数字化测速测距接收机设计并实现全数字化超窄带锁相环。
Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.
分析了锁相环的基本原理和实现，并对射频电路设计理论和阻抗匹配问题进行了探究。
A new method is presented for analyzing the acquisition behavior of second-order PLL with sinusoidal phase detector in the absence of noise.
本文给出了一种计算无噪声时具有正弦鉴相器的二阶锁相环捕捉特性的新方法，求得了每个差频周期的平均角频率牵引量。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
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