• The gappy clock is recovered by the PLL.

    利用锁相环完成恢复

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  • PLL is used for generating carry synchronization signal.

    采用平方环实现载波同步信号的提取。

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  • Outputs serial data transferred from the PLL to the controller.

    PLL输出串行信号控制器

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  • PLL circuit is adopted in order to control video signal synchronization.

    系统采用相环路控制视频同步

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  • DDS-driven PLL frequency synthesizer architecture is given in this paper.

    给出一种基于DDS驱动PLL频率综合器结构

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  • The PLL has different un-locked threshold value in different jamming model.

    环路不同干扰样式下的失锁门限不尽相同

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  • High stability PLL-modulator and high sensitivity receiving demodulator are introduced.

    介绍了稳定锁相调制灵敏度接收解调

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  • In the field of communications, PLL synthesizers playing an increasingly important role.

    通信领域锁相环频率合成器越来越重要的角色。

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  • It also give an improved method for PLL (phase locked loop) to extract coherent carrier.

    本文相干载波提取中的锁相环提出一种改进方法

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  • The authors propose an improved phased locked loop (PLL) architecture with dual control paths.

    提出一种改进控制通路锁相环结构

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  • The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.

    定量分析了数字式输出信号相位抖动

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  • In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

    为了尽量减少抖动锁相环建议避免测试输出积极信号

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  • A new phase noise estimate method for millimeter wave double PLL frequency synthesizer is presented.

    提出一种新的毫米波双环锁相相位噪声估测方法

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  • This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.

    本机工作UHF频率采用PLL锁相环电路,预设256个可选择使用频率。

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  • The working state of all points in the PLL can be visibly displayed, with high ability in aid analyses.

    相环路各工作状态可用图形直观显示,辅助分析能力

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  • The nonlinear characteristics of PLL system are analyzed comprehensively in this thesis for the first time.

    首次电机锁相控制系统非线性问题进行较全面研究工作。

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  • In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.

    锁相环频率合成器中前置分频器一个速度瓶颈

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  • A computer aid analysis method for PLL of block-linking type facing systematic mathematical models is proposed.

    提出了一面向系统数学模型模块连接锁相环路计算机辅助分析方法

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  • DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.

    PLL混合频率合成技术综合两者优点成为现今频率合成领域重要研究方向。

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  • In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.

    本文叙述了一个微机控制锁相环频率合成数字调谐系统原理设计

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  • The PLL full synchronization video detector circuit is educed by feature and troubles of quasi-synchronization video detector.

    同步视频检波特点及其存在的问题引出相环( PLL完全同步视频检波电路

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  • The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.

    微型计算机控制(PLL)对计量光栅信号进行数字

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  • When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation.

    水平同步振动者频率之间巧合被发现的时候,搜寻正常PLL操作代替

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  • Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL.

    我们准备相环找到配置之前,首先要考虑如何找到锁相环的所有配置。

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  • The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.

    本文正是为数字化测速测距接收机设计实现数字化超窄带

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  • Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.

    分析锁相环基本原理实现射频电路设计理论阻抗匹配问题进行了探究。

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  • A new method is presented for analyzing the acquisition behavior of second-order PLL with sinusoidal phase detector in the absence of noise.

    本文给出了一种计算噪声时具有正弦鉴相器相环捕捉特性方法,求得了每个差频周期的平均角频率牵引量。

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  • Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.

    跟踪频率斜升信号时产生的稳态相差致使环路失锁,接收机无法锁定载波信号。

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  • Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).

    然后介绍(PLL)的基本结构相位模型频率响应噪声杂散性能

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  • Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).

    然后介绍(PLL)的基本结构相位模型频率响应噪声杂散性能

    youdao

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