This paper introduces a method of FSK modulation and demodulation using CMOS phase locked-loop chip CD4046.
文章介绍了一种利用CMOS锁相环芯片CD 4046实现FSK信号调制与解调的方法。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
Because of the fading characteristic in troposcatter channel, the mechanism of traditional phase locked loop is difficult to achieve the effect in troposcatter communication.
由于对流层散射信道存在严重的衰落现象，故而传统的锁相环机制在散射通信中往往难以奏效。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
To aim at the defect of traditional sampled data acquisition scheme, a new method of realizing sampled data acquisition by phase locked loop is presented.
针对传统的取样式数据采集方案存在的缺点，提出一种利用锁相环实现取样式数据采集的新方法。
The principle of voltage linear digital triggering of thyristor by EPROM is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop .
描述了用EPROM实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。
High precise measuring and tracking of carrier frequency-deviation is necessary to the realization of a high performance phase locked loop in carrier recovery.
载波恢复中高精度的频偏检测与跟踪是高性能锁相位环路实现的必要条件。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.
利用锁相环路原理提出锁相自动准同期控制方案。
The basic principle of phase locked loop (PLL) has been introduced, and the transmission function of the phase noises of every part of PLL has been analyzed.
介绍了锁相环的基本原理，分析了锁相环各部分电路相位噪声的传递函数。
Now the full integrated PLL (phase locked loop) chip is used widely in radio frequency circuit.
全集成锁相环芯片目前在射频电路中应用很广泛。
The design of precise position tracking loop for DRTS with fast digital phase-locked loop is described.
本文提出一种用于光盘径向伺服系统的带有快速数字锁相环的精密位置跟踪环路的设计方案。
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
The software phase-locked loop (SPLL) technology in the steady speed control of permanent magnet brushless DC motor (BLDCM) in gyro was discussed.
研究了软件锁相环技术在陀螺用无位置传感器无刷直流电机稳速控制系统中的应用。
The industrial grating signals can be digital frequency multiplication with a phase-locked loop (PLL) controlled by a microcomputer.
用微型计算机控制锁相环(PLL)可对计量光栅信号进行数字倍频。
Signal demodulation of automatic block with audio frequency shift modulated track circuits was implemented with phase-locked loop (PLL) technique and a singe chip microcomputer.
利用锁相环(LL)窄带跟踪特性，与单片机结合，实现自动闭塞系统移频信号解调。
The use of phase-locked loop technology makes the sampling frequency synchronously follow the signal frequency and improves the calculation accuracy of sampling data.
运用锁相环技术使采样频率同步跟踪信号频率，提高采样数据计算的准确性。
FIG. 1 illustrates an example of a phase-locked loop (PLL) that can include techniques of the present invention.
图1图示说明可以包括本发明技术的相锁环(PLL)的示例。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
The fluorescence thermometry system in which the fluorescence lifetime is detected by phase-locked loop is established, and the specific phase-locked loop circuit is designed.
设计具体的锁相环电路，并建立利用锁相环技术检测荧光寿命的荧光温度传感器系统。
According to the theory of phase-locked loop, we use reflected photoelectric sensor to carry out the color recognition.
根据锁相环的原理，使用反射式光电传感器实现了系统的颜色识别。
Compared with traditional phase - locked loop, the design has a convenient programming and reliable operating performance.
与传统锁相环相比，该设计编程方便，工作可靠。
Subsequently, the detailed discussion of the software phase-locked loop technology and network process, the composition of the phase-locked loop circuit, the working principle of the study.
随后，本文详细讨论了并网过程中的软件锁相环技术，对锁相环电路的组成、工作原理进行了研究。
In this scheme, the output of the first phase-locked loop (PLL1) ACTS as the reference of DDS, and then the output of DDS stimulates the second phase-locked loop (PLL2).
此方案把第一个锁相环(PLL1)的输出作为DDS的参考信号，再用DDS的输出去激励第二个锁相环(PLL2)。
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
The operating principle and performance of fractional-N phase locked loop (FNPLL) are described in detail, and the methods of suppressing FNPLL phase modulation sideband are introduced.
较详细介绍了分数分频锁相环的工作原理和特性，以及抑制分数分频锁相环相位调制边带的方法。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
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