A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal.
相位比较器比较基准时钟和输出时钟的相位，并输出相位比较信号。
This paper describes a new method, Doppler heterodyne measurement method of surface profile, using a simultaneous phase comparator.
本文提出了一种新的方法，多普勒外差法测量表面面形，并首次提出和制作了同步相位计。
The theory to extract angular error is described and the realization of millimeter radar's digital phase comparator and extracting method of angular error's sign are discussed.
论述了如何利用和差三通道的一维距离像来获取三维图像的实现方法。
Simulations have been done through adjusting parameters such as input signal amplitude, feedback gain, amplifier gain, comparator gain and the position of the phase compensator.
改变输入信号幅度、反馈增益系数、放大器增益、比较器增益等参数以及相位补偿器的位置进行了仿真。
The digital comparator designed with FPGA generates several PWM current waveform synchronously, to realize the step angles even division control for four-phase stepping motor.
并通过FPGA设计的数字比较器，同步产生多路PWM电流波形，实现对四相步进电动机转角进行均匀细分控制。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The present invention comprises a phase and frequency comparator and a comparing module.
该频率比较器包括一相位-频率检测器以及一比较模块。
The magnitude comparator designed with FPGA generates several PWM current waveform synchronously, to realize the step angles even division control for four-phase stepping motor.
并通过FPGA设计的数字比较器，同步产生多路PWM电流波形，实现对四相步进电动机转角进行均匀细分控制。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
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