The paper analyzes the phase-lock technique of serial resonant inverter with power MOSFET as switching device.
研究了以功率MOSFET为开关管的串联谐振逆变器的频率跟踪问题。
The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.
锁相接收机的作用是重建原信号而尽可能地去除噪声。
The phase-lock technique is widely used in many fields, such as modulation and demodulation circuit and frequency synthesizer circuit.
锁相技术在调制和解调、频率合成电路等很多领域应用极其广泛。
In general, the design of phase-lock loops has been done by a combination of linear analysis, phase plane plots, rule of thumb, and simulation.
锁相环一般采用线性分析，相平面图，近似计算法以及计算机模拟来设计。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
The circuits used are Chua 'circuit and phase lock loop.
所用的电路为蔡氏电路和锁相环电路。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
数字锁相环路（DPLL）是数字相干解调技术的核心。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
Phase lock loop and benchmark resistance compensating technologies were used to improve the detection precision, the error was less than 10%.
通过锁相放大技术及基准电阻补偿方法提高了测量的精度，误差在10%以内。
This paper mainly discusses the design and the application of the IGBT phase lock control circuit controlled by the induction heating power supply.
本文主要介绍IGBT锁相控制电路在感应加热电源控制系统中的设计和应用。
This paper gives a detailed analysis of the principle of the phase lock circuit, one of the most important parts of the QF1052B Standard Signal Generator and provides some methods of checking it.
本文详细分析了QF1052B型标准信号发生器锁相环部分的基本组成及其工作原理，并提出了对此部分电路的检测方法。
By using a double phase lock in amplifier to measure the AC strain, the measurement error can be decreased to 0.4% of the total measurement range.
如果使用双相位锁相放大器测量交变的被测量，误差将减小到全量程的0.4%以内。
We have mainly researched two FM signal demodulation techniques called Frequency Spectrum Separation and Phase Lock Loop in the first part.
一次解调中研究了频谱分离法和锁相法两种实现鉴频的技术。
Digital phase lock loops are widely adapted in nowadays communication systems. However, it is difficult to design the loop parameter precisely.
数字锁相环在实际通信系统中应用广泛，但其精确的环路参数设计比较困难。
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。
Due to the frequency pulling of FLL, the passband of the filter in PLL can be made very narrow to suppress the noise, and the PLL can lock carrier's phase with high accuracy.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
This new algorithm can detect and repair cycle slips after loss of lock within 3 seconds so as to avoid the effect of cycle slips on smooth pseudo distance of carrier phase.
检验证明该方法能够准确可靠地探测并修复失锁3秒以内的周跳，避免了周跳对载波相位平滑伪距的影响。
However, process mismatches and other factors can cause a small phase difference between the phase of RCLK and the phase of FCLK even when PLL 100 is lock mode.
然而，即使PLL 100处于锁定模式，过程失配和其他因素也可能引起RCLK相位和FCLK相位之间小的相位差。
So, after reservoir watering out as edge water and bottom water enters, the gas phase permeability will decrease greatly, and strong water lock effect will happen.
因此，当边水和底水进入储层发生水淹后，气相渗透率将极大降低，存在较强的水锁效应。
It is noted that the minimum mean square error (MMSE) detector often loses phase to lock a desired signal when the desired signal dips into a deep fade.
在实际通信系统中当信号处于深衰落时，最小均方误差(MMSE)检测器经常失去对信号的相位跟踪。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
In frequency synthesis by phase lock, the loop gain will vary by the same amount due to this effect, which generally im - pedes optimization of loop performance.
在锁相频率合成器中，由于压控灵敏度的变化，环路增益也将产生同样大小的变化，这就妨碍了环路特性的最佳化。
The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.
使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。
The phase lock loop is a feedback control system that makes two telecommunication signals' phase synchronization, suitable to the synchronous trigger circuit of the convertor device.
锁相环路是完成两个电信号相位同步的反馈控制系统，适宜于变流装置的同步触发电路之中。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。
Used lock-in amplifier SR844 for hardware phase detection and compared with software detection.
利用锁相放大器SR844对产生的信号进行模拟鉴相，并同软件鉴相结果比较分析；
This study aims at investigating the lock-in phenomenon, fluctuating lift and the phase shift between fluctuating lift and displacement of the oscillating cylinder.
文章重点研究了较高振幅振动柱的锁定现象、波动升力与柱位移之间的相位变化，讨论了方柱涡激振荡、驰振和气动稳定性问题。
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