A fast and exact fault simulator is proposed for path delay faults.
论文提出了一个针对路径延迟故障的快速并精确的故障模拟器。
The improved lifting scheme is adopted to reduce the critical path delay.
采用改进的提升算法，减少了关键路径上的延时。
The carry skip adder optimal block sizes can minimize critical path delay.
优化方块分配的进位跳跃加法器可以缩短关键路径的延时。
Because of the decreased critical path delay, the conversion can be implemented in a single cycle.
关键路径延时的减小，使这一转换可以在单周期内完成。
The test generation algorithm for non-robust path delay fault in combinational circuits is studied.
研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed.
最后，我们提出一个利用路径延迟惯性原理，来测试系统电路连线之串音障碍的新测试方法。
Through the synthesis of MAC circuit, it validates that the ideas and methods presented in the paper do well to reduce the critical path delay and circuit gates.
电路综合实验表明采用本文所提出思想和方法可以有效减少MAC关键路径时延和电路门数。
This paper presents an approach to delay testing with duplicating variable observation points, which provides a high path delay fault coverage by testing a small number of paths.
本文提供了一种使用双倍可变观测点进行时滞测试的方法，保证了只需要测试少量通路就能完成整个电路的时滞测试。
MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.
对MCNC标准单元测试电路中组合和时序电路的实验结果显示， 电路经过时延驱动优化布局后的最大路径时延最多减少了31%。
Simulation shows co-channel interference and maximum multi-path delay spread have significant impact on the BER performance and PDMRC gives the best performance in most common environment.
仿真表明同信道干扰与最大多径延迟扩展对系统性能影响很大，在通常情况下采用PDMRC具有最好的性能。
Due to the strong spatial inhomogeneity and temporal variability of atmosphere, especially water vapor , accurate modeling of path delay in GPS signals is necessary for high -accuracy position.
由于大气分布不均和不断的变化，尤其是大气中的水汽影响，使建立无线电信号路径延迟的精确模型在GPS高精度定位中非常必要。
A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题，提出了基于神经网络的数字电路路径时滞故障测试生成算法。
OFDM is a high transmission technology in the wireless propagation environment. It is fitted to transmit high-speed data in the wireless channel which has multi-path delay and Doppler frequency shift.
OFDM是一种无线传播环境下的高速传输技术，适合在多径传播和多普勒频移的无线信道中传输高速数据。
In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.
文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。
In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.
文章在静态时序分析的基础上，提出了一种利用关键路径时延信息提高FPGA分割效率的方法。
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