A new high-speed implementation of SHA which is based on FPGA is proposed, combining two popular hardware optimization techniques, namely "partially unrolling" and "path optimization".
结合“循环打开”和“路径优化”两大硬件优化技术，提出基于FPGA的SHA系列加密算法的高速实现方案。
A new high-speed implementation of SHA which is based on FPGA is proposed, combining two popular hardware optimization techniques, namely "partially unrolling" and "path optimization".
结合“循环打开”和“路径优化”两大硬件优化技术，提出基于FPGA的SHA系列加密算法的高速实现方案。
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