A partial scan algorithm for BIST, which combines the structure analysis and testability analysis, is presented in this paper.
提出了一种在内建自测试(BIST)中进行部分扫描的算法，此算法综合了电路的结构分析和可测性分析。
An integrated circuit is described as comprising a plurality of logic elements (LEs), each of which having a plurality of outputs, and a partial scan register.
一种集成电路，包括多个逻辑元件(LE)和一个部分扫描寄存器，每个逻辑元件具有多个输出。
Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.
在分析全扫描内建自测试(BIST)过高测试功耗原因的基础上，提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗BIST。
Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.
在分析全扫描内建自测试(BIST)过高测试功耗原因的基础上，提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗BIST。
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