In order to realize the normal data communication between each part of the system, we adopt serial communication and parallel communication technology, and design the communication protocol.
为了实现系统各部分之间正常的数据通信，本课题采用了常用的串行通讯和并行通讯技术，并制定了一套完整的通讯协议。
This paper analyzes shortcoming of microprocessors parallel extension and advances serial extension to optimize the system design.
分析了单片机系统并行扩展的缺点，提出用串行扩展来优化单片机系统。
Shortcoming of microcomputer system's parallel extension is analyzed, and serial extension to optimize design of system is advanced.
分析单片机系统并行扩展的缺点，提出用串行扩展来优化单片机系统。
A test system which can perform the function of multi signals parallel acquisition and serial transmission was designed in this paper.
设计了一个能够进行多个信号并行采集、串行发送的检测系统。
In the last unfavorable situation this is a minor dysfunction of the system and the microcontroller is still able to dialog with a test station via a serial or parallel interface.
在最不顺的情况下，这只是系统的小故障，单片机仍然能够通过串行或并行口与测试设备对话。
In power system, it can excite partial parallel resonance or serial resonance, enlarge the harmonic wave, trigger relay protection system in error and disturb electric power energy metering equipment.
在电力系统，它可以刺激局部并联谐振或串联谐振，放大谐波，引发继电保护系统误差和扰乱电力能源计量设备。
An algorithm for kinematical analysis of this coupled system with both serial and parallel conections is presented.
对于此类串并联复合的系统提出了一种运动学分析方法。
The system adopted AT89S51 CPU, which can finish controlling, computing, storing and communication functions through extending program memory, data memory, serial port and parallel port.
本系统CPU采用AT 89s51，通过程序存贮器、数据存贮器、串口和并口的扩展，可以完成控制、计算、存贮和通讯等功能。
The system model was depicted by queuing theory, serial as well as parallel queuing model were employed in setting up the system model.
该模型采用排队论进行描述，利用串行与并行排队模型对系统原型进行建模；
A multiplex control system based on serial entry and output in series-parallel mixed mode is designed.
设计一种以串行输入为基础，串并混合方式输出的多路控制系统。
This demodulation system also has serial port, parallel port, JTAG port, and can display signal wave in LCD.
本解调系统还拥有串口、并口等通信接口以及JTAG调试接口。自带lcd，可以动态显示解调后的信号波形。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
Especially, the efficiency of the parallel algorithm is almost twice of serial algorithm when system has dual CPUs.
特别是在双cpu情况下，并行算法的效率接近顺序算法的两倍。
The system can insure the conversion between the Serial Communication and network interface, and finite samples multi-channel parallel collection, and real-time display and data conservation function.
该系统实现串口通信与网络接口的转化，有限点多通道并行采集，实时显示及数据保存功能。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
To make a choice between composite coding or component coding and between parallel interface or serial interface is crucial in the design of a full digital TV production system.
在全数字电视制作系统的设计中，选择数字编码方式和接口形式是关键。
To make a choice between composite coding or component coding and between parallel interface or serial interface is crucial in the design of a full digital TV production system.
在全数字电视制作系统的设计中，选择数字编码方式和接口形式是关键。
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