XMLNSC validation considerably out-performs MRM validation too, as the architecture of the new high performance XML parser is optimized for the model-driven scenario.
XMLNSC验证的性能也在相当大的程度上胜过 MRM 验证，因为新的高性能XML解析器的体系结构针对模型驱动的场景进行了优化。
RHEL3 provides a 2.4.21 Linux kernel optimized for the POWER architecture.
RHEL3 的2.4.21Linux内核为POWER体系结构进行了优化。
Each Digital Realty Trust Turn-Key Datacentre facility is physically secure and features a state-of-the-art power and cooling architecture that has been optimized for green operation.
每个数字房地产信托交钥匙数据中心的设施物理上是安全的，装备了为绿色节能优化的最先进的电源和散热架构。
It is also optimized for the Intel Nehalem processor micro-architecture.
它还针对Intel的Nehalem处理器微型架构进行了优化。
A new approach is presented of the eigen-structure subspace algorithms, the problem of ambiguous estimation in the original algorithm is solved and array architecture is optimized.
提出了改进的特征结构子空间算法，采用二维联合估计方法，解决了原算法存在的角度估计模糊问题。
In addition to tweaking existing pages, you should consider adding more optimized pages to your site's architecture.
除了调整现有的网页，你应该考虑增加您的网站页面优化的架构。
This paper proposes a kind of optimized TSS algorithm and its implementation based on candidate groups hardware architecture.
提出一种改进的三步搜索算法，并采用基于候选组处理的硬件结构实现。
Basing on that, distributed tracking system is optimized so that its tracking accuracy would approach that of centralized tracking system, and its architecture maintains original merits as well.
在此基础上，对分布式融合跟踪系统进行优化，在保留系统原有优点的同时，使其跟踪精度更接近集中式融合跟踪系统。
In the lifecycle of developing a software, the architecture is optimized by constant iteration.
在整个开发的生命周期中，软件架构是经过许多次的迭代并不断进化的。
IP-Explorer Technology - Heuristic-driven selection of hardware architecture at the algorithmic level to produce system-optimized designs.
IP -浏览器技术-算法级硬件架构的启发性驱动选择生成系统优化的设计。
Some specific architecture is allowed to be optimized in VIP stack.
VIP协议栈允许针对特定的体系结构进行优化。
Furthermore, this ADC architecture is optimized by converting the most significant bit to analog domain. This method can reduce the precision requirement of the extra DAC to 2~3 bits.
进一步，文章对该结构进行优化，通过把补偿信号的高比特位的值转换到模拟域，将引入的DAC精度降低到2~3个比特，从而进一步降低了该结构的设计复杂度和功耗。
Furthermore, this ADC architecture is optimized by converting the most significant bit to analog domain. This method can reduce the precision requirement of the extra DAC to 2~3 bits.
进一步，文章对该结构进行优化，通过把补偿信号的高比特位的值转换到模拟域，将引入的DAC精度降低到2~3个比特，从而进一步降低了该结构的设计复杂度和功耗。
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