In this thesis, the design and FPGA implementation result of a finite field polynomial multiplier is presented, whose arithmetic architecture is based on the number theoretic transform.

研究设计了一种具有自主知识产权的高速、高精度的有限域多项式相乘运算核。

youdao

In this thesis, the design and FPGA implementation result of a finite field polynomial multiplier is presented, whose arithmetic architecture is based on the number theoretic transform.

研究设计了一种具有自主知识产权的高速、高精度的有限域多项式相乘运算核。

youdao